產品詳細資料

Configuration 2:1 SPDT Number of channels 4 Power supply voltage - single (V) 5, 12, 16, 20, 36, 44 Power supply voltage - dual (V) +/-10, +/-15, +/-18, +/-22, +/-5 Protocols Analog Ron (typ) (Ω) 3.5 CON (typ) (pF) 76 ON-state leakage current (max) (µA) 0.008 Supply current (typ) (µA) 45 Bandwidth (MHz) 100 Operating temperature range (°C) -40 to 125 Features 1.8-V compatible control inputs, Break-before-make, Fail-safe logic, Integrated pulldown resistor on logic pin Input/output continuous current (max) (mA) 400 Rating Catalog Drain supply voltage (max) (V) 44 Supply voltage (max) (V) 44 Negative rail supply voltage (max) (V) -44
Configuration 2:1 SPDT Number of channels 4 Power supply voltage - single (V) 5, 12, 16, 20, 36, 44 Power supply voltage - dual (V) +/-10, +/-15, +/-18, +/-22, +/-5 Protocols Analog Ron (typ) (Ω) 3.5 CON (typ) (pF) 76 ON-state leakage current (max) (µA) 0.008 Supply current (typ) (µA) 45 Bandwidth (MHz) 100 Operating temperature range (°C) -40 to 125 Features 1.8-V compatible control inputs, Break-before-make, Fail-safe logic, Integrated pulldown resistor on logic pin Input/output continuous current (max) (mA) 400 Rating Catalog Drain supply voltage (max) (V) 44 Supply voltage (max) (V) 44 Negative rail supply voltage (max) (V) -44
TSSOP (PW) 20 41.6 mm² 6.5 x 6.4 WQFN (RRQ) 20 16 mm² 4 x 4
  • Latch-up immune
  • Dual supply range: ±4.5 V to ±22 V
  • Single supply range: 4.5 V to 44 V
  • Low on-resistance: 3 Ω
  • Low charge injection: 3 pC
  • High current support: 400 mA (maximum)
  • –40°C to +125°C operating temperature
  • 1.8 V logic compatible inputs
  • Fail-safe logic
  • Rail-to-rail operation
  • Bidirectional signal path
  • Break-before-make switching
  • Latch-up immune
  • Dual supply range: ±4.5 V to ±22 V
  • Single supply range: 4.5 V to 44 V
  • Low on-resistance: 3 Ω
  • Low charge injection: 3 pC
  • High current support: 400 mA (maximum)
  • –40°C to +125°C operating temperature
  • 1.8 V logic compatible inputs
  • Fail-safe logic
  • Rail-to-rail operation
  • Bidirectional signal path
  • Break-before-make switching

The TMUX7234 is a complementary metal-oxide semiconductor (CMOS) multiplexer with latch-up immunity. The TMUX7234 contains four independently controlled SPDT switches with an EN pin to enable or disable all four channels. The device supports single supply (4.5 V to 44 V), dual supplies (±4.5 V to ±22 V), or asymmetric supplies (such as VDD = 12 V, VSS = –5 V). The TMUX7234 supports bidirectional analog and digital signals on the source (Sx) and drain (D) pins ranging from VSS to VDD.

All logic control inputs support logic levels from 1.8 V to VDD, ensuring both TTL and CMOS logic compatibility when operating in the valid supply voltage range. Fail-Safe Logic circuitry allows voltages on the control pins to be applied before the supply pin, protecting the device from potential damage.

The TMUX72xx family provides latch-up immunity, preventing undesirable high current events between parasitic structures within the device typically caused by overvoltage events. A latch-up condition typically continues until the power supply rails are turned off and can lead to device failure. The latch-up immunity feature allows the TMUX72xx family of switches and multiplexers to be used in harsh environments.

The TMUX7234 is a complementary metal-oxide semiconductor (CMOS) multiplexer with latch-up immunity. The TMUX7234 contains four independently controlled SPDT switches with an EN pin to enable or disable all four channels. The device supports single supply (4.5 V to 44 V), dual supplies (±4.5 V to ±22 V), or asymmetric supplies (such as VDD = 12 V, VSS = –5 V). The TMUX7234 supports bidirectional analog and digital signals on the source (Sx) and drain (D) pins ranging from VSS to VDD.

All logic control inputs support logic levels from 1.8 V to VDD, ensuring both TTL and CMOS logic compatibility when operating in the valid supply voltage range. Fail-Safe Logic circuitry allows voltages on the control pins to be applied before the supply pin, protecting the device from potential damage.

The TMUX72xx family provides latch-up immunity, preventing undesirable high current events between parasitic structures within the device typically caused by overvoltage events. A latch-up condition typically continues until the power supply rails are turned off and can lead to device failure. The latch-up immunity feature allows the TMUX72xx family of switches and multiplexers to be used in harsh environments.

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類型 標題 日期
* Data sheet TMUX7234 44 V, Low Ron, 2:1, 4 Channel Precision Switches with Latch-Up Immunity and 1.8 V Logic datasheet (Rev. G) PDF | HTML 2024年 7月 9日
Application note How to Handle High Voltage Common Mode Applications using Multiplexers PDF | HTML 2022年 10月 3日
Application note Using Latch Up Immune Multiplexers to Help Improve System Reliability (Rev. A) 2021年 9月 20日
Application brief Precision Multiplexers Reducing Barriers in an Industrial Environment PDF | HTML 2021年 5月 21日

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開發板

TMUXRTJ-RRQEVM — 適用於 20 針腳 RTJ 和 RRQ QFN 封裝的通用 TMUX 評估模組

TMUXRTJ-RRQEVM 可對 TI 的 TMUX 產品系列進行快速原型設計和 DC 特性分析,這些產品使用 20 接腳 RTJ 或 RRQ 封裝 (QFN),並且額定用於高電壓操作。

使用指南: PDF | HTML
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介面轉接器

LEADED-ADAPTER1 — 適用於快速測試 TI 的 5、8、10、16 及 24 針腳引線封裝的表面貼裝至 DIP 接頭適配器

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

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介面轉接器

LEADLESS-ADAPTER1 — 用於測試 TI 的 6、8、10、12、14、16 和 20 針腳無引線封裝的表面貼裝至 DIP 接頭適配器

The EVM-LEADLESS1 board allows for quick testing and bread boarding of TI's common leadless packages.  The board has footprints to convert TI's DRC, DTP, DQE, RBW, RGY, RSE, RSV, RSW RTE, RTJ, RUK , RUC, RUG, RUM,RUT and YZP surface mount packages to 100mil DIP headers.
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模擬型號

TMUX7234 IBIS Model

SCDM264.ZIP (52 KB) - IBIS Model
模擬型號

TMUX72XX-8SW - TMUX723X PSPICE Model

SCDM303.ZIP (29 KB) - PSpice Model
封裝 針腳 CAD 符號、佔位空間與 3D 模型
TSSOP (PW) 20 Ultra Librarian
WQFN (RRQ) 20 Ultra Librarian

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