TPA2032D1
- Maximize Battery Life and Minimize Heat
- 0.5–µ Shutdown Current
- 3.0–mA Quiescent Current
- High Efficiency Class–D
- 88% at 400mW at 8
- 80% at 100mW at 8
- Three Fixed Gain Versions
- TPA2032D1 has a gain of 2 V/V (6dB)
- TPA2033D1 has a gain of 3 V/V (9.5dB)
- TPA2034D1 has a gain of 4 V/V (12dB)
- Only One External Component Required
- Internal Matched Input Gain and Feedback Resistors for Excellent PSRR and CMRR
- Optimized PWM Output Stage Eliminates LC Output Filter
- PSRR (–75 dB) and Wide Supply Voltage (2.5 V to 5.5 V) Eliminates Need for a Dedicated Voltage Regulator
- Fully Differential Design Reduces RF Rectification and Eliminates Bypass Capacitor
- CMRR (–69 dB)Eliminates Two Input Coupling Capacitors
- Thermal and Short–Circuit Protection
- Pinout Very Similar to TPA2010D1
- Wafer Chip Scale Packaging (WCSP)
- NanoFree Lead–Free (Pb–Free: YZF)
- APPLICATIONS
- Ideal for Wireless Handsets, PDAs, and other mobile devices
The TPA2032D1 (2V/V gain), TPA2033D1 (3V/V gain), and TPA2034D1 (4V/V gain) are 2.75W high efficiency filterfree classD audio power amplifiers, each in an approximately 1.5mm × 1.5mm wafer chip scale package (WCSP) that requires only one external component. The pinout is the same as the TPA2010D1 except that the external gain setting input resistors required by the TPA2010D1 are integrated into the fixed gain TPA203xD1 family.
Features like 75dB PSRR and improved RFrectification immunity with a very small PCB footprint (WCSP amplifier plus single decoupling cap) make the TPA203xD1 family ideal for wireless handsets. A fast startup time of 3.2 ms with minimal pop makes the TPA203xD1 family ideal for PDA applications.
In wireless handsets, the earpiece, speaker phone, and melody ringer can each be driven by a TPA203xD1. The TPA203xD1 family has a low 27µV noise floor, Aweighted.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | 2.75-W Fixed Gain Mono Filter-Free Class-D Audio Power Amplifier datasheet | 2006年 6月 21日 | |
User guide | TPA2032/33/34D1EVM - User Guide (Rev. A) | 2006年 6月 26日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
DSBGA (YZF) | 9 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點