5 Small IC Packaging

Integrated circuit packaging technology must keep pace with semiconductor wafer fabrication as process technology advances. TI has released flip-chip on leadframe packaging that reduce package footprint, power loss, and parasitic effects. Traditional bond wires are replaced with copper posts attached directly to the leadframe which shortens current path from the IC to the lead frame, which allows a larger die in the small package cavity, reduced package resistance, and reduced parasitic package inductance loops. Consider the 6-A TPS566335, housed in a small 2x3mm QFN package. Figure 5-1 shows ample pins for power conversion and I/O features while maintaining a 0.5mm pin pitch, allowing simplified circuit board manufacturing.

Figure 5-1 TPS566335 in 2x3mm QFN Package