CDC339

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Takttreiber für 1 bis 8 Leitungen mit Tri-State-Ausgängen

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Datenblatt

document-pdfAcrobat CDC339 Clock Driver With 3-State Outputs datasheet (Rev. A) (Englisch)

CDC339

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Function

Clock divider

Output frequency (max) (MHz)

80

Number of outputs

8

Output supply voltage (V)

5

Core supply voltage (V)

5

Output skew (ps)

0.75

Features

Pin programmable

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

TTL

Input type

TTL

Function

Clock divider

Output frequency (max) (MHz)

80

Number of outputs

8

Output supply voltage (V)

5

Core supply voltage (V)

5

Output skew (ps)

0.75

Features

Pin programmable

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

TTL

Input type

TTL

SOIC (DW)

20

131.84 mm² 12.8 x 10.3

SSOP (DB)

20

56.16 mm² 7.2 x 7.8

Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
TTL-Compatible Inputs and Outputs
Distributes One Clock Input to Eight Outputs
- Four Same-Frequency Outputs
- Four Half-Frequency Outputs
Distributed V_CCand Ground Pins Reduce Switching Noise
High-Drive Outputs (−48-mA I_OH, 48-mA I_OL)
State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Power Dissipation
Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages

Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
TTL-Compatible Inputs and Outputs
Distributes One Clock Input to Eight Outputs
- Four Same-Frequency Outputs
- Four Half-Frequency Outputs
Distributed V_CCand Ground Pins Reduce Switching Noise
High-Drive Outputs (−48-mA I_OH, 48-mA I_OL)
State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Power Dissipation
Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages

The CDC339 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring synchronized output signals at both the primary clock frequency and one-half the primary clock frequency. The four Y outputs switch in phase and at the same frequency as the clock (CLK) input. The four Q outputs switch at one-half the frequency of CLK.

When the output-enable (OE) input is low and the clear (CLR) input is high, the Y outputs follow CLK and the Q outputs toggle on low-to-high transitions of CLK. Taking CLR low asynchronously resets the Q outputs to the low level. When OE is high, the outputs are in the high-impedance state.

The CDC339 is characterized for operation from −40°C to 85°C.

The CDC339 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring synchronized output signals at both the primary clock frequency and one-half the primary clock frequency. The four Y outputs switch in phase and at the same frequency as the clock (CLK) input. The four Q outputs switch at one-half the frequency of CLK.

When the output-enable (OE) input is low and the clear (CLR) input is high, the Y outputs follow CLK and the Q outputs toggle on low-to-high transitions of CLK. Taking CLR low asynchronously resets the Q outputs to the low level. When OE is high, the outputs are in the high-impedance state.

The CDC339 is characterized for operation from −40°C to 85°C.

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	Typ	Titel		Datum
*	Data sheet	CDC339 Clock Driver With 3-State Outputs datasheet (Rev. A)		14 Mai 2020

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CDC339

Takttreiber für 1 bis 8 Leitungen mit Tri-State-Ausgängen

CDC339

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