CDCLVD110
1 bis 10 LVDS-Taktpuffer bis zu 900 MHz mit minimalem Versatz für Taktverteilung
Drop-In-Ersatz mit gegenüber dem verglichenen Baustein verbesserter Funktionalität
CDCLVD110
- Low-Output Skew <30 ps (Typical) for Clock-Distribution Applications
- Distributes One Differential Clock Input to 10 LVDS Differential Clock Outputs
- VCC range 2.5 V ±5%
- Typical Signaling Rate Capability of Up to 1.1 GHz
- Configurable Register (SI/CK) Individually Enables Disables Outputs,
Selectable CLK0, CLK0 or CLK1, CLK1 Inputs - Full Rail-to-Rail Common-Mode Input Range
- Receiver Input Threshold ±100 mV
- Available in 32-Pin LQFP Package
- Fail-Safe I/O-Pins for VDD = 0 V (Power Down)
The CDCLVD110 clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0, Q9) with minimum skew for clock distribution. The CDCLVD110 is specifically designed for driving 50-
transmission lines.
When the control enable is high (EN = 1), the 10 differential outputs are programmable in that each output can be individually enabled/disabled (3-stated) according to the first 10 bits loaded into the shift register. Once the shift register is loaded, the last bit selects either CLK0 or CLK1 as the clock input. However, when EN = 0, the outputs are not programmable and all outputs are enabled.
The CDCLVD110 is characterized for operation from -40°C to 85°C.
Not Recommended for New Designs. Use CDCLVD110A as a Replacement.
Technische Dokumentation
| Typ | Titel | Datum | ||
|---|---|---|---|---|
| * | Data sheet | Programmable Low-Voltage 1:10 LVDS Clock Driver datasheet (Rev. C) | 14 Jan 2008 |
Bestellen & Qualität
- RoHS
- REACH
- Bausteinkennzeichnung
- Blei-Finish/Ball-Material
- MSL-Rating / Spitzenrückfluss
- MTBF-/FIT-Schätzungen
- Materialinhalt
- Qualifikationszusammenfassung
- Kontinuierliches Zuverlässigkeitsmonitoring
- Werksstandort
- Montagestandort