DRV8343-Q1

AKTIV

12-bis-24-V-Batterie-3-Phasen-Smart-Gate-Treiber mit Strom-Shunt-Verstärkern für die Automobilind

Produktdetails

Rating Automotive Architecture Gate driver Control interface 1xPWM, 3xPWM, 6xPWM Gate drive (A) 1 Vs (min) (V) 5.5 Vs ABS (max) (V) 65 Features Current sense Amplifier, Hardware Management I/F, Independent FET Control, SPI/I2C, Smart Gate Drive Operating temperature range (°C) -40 to 125
Rating Automotive Architecture Gate driver Control interface 1xPWM, 3xPWM, 6xPWM Gate drive (A) 1 Vs (min) (V) 5.5 Vs ABS (max) (V) 65 Features Current sense Amplifier, Hardware Management I/F, Independent FET Control, SPI/I2C, Smart Gate Drive Operating temperature range (°C) -40 to 125
HTQFP (PHP) 48 81 mm² 9 x 9
  • AEC-Q100 qualified for automotive applications
    • Temperature grade 1: –40°C ≤ TA ≤ 125°C
  • Three independent half-bridge gate driver
    • Dedicated source (SHx) and drain (DLx) pins to support independent MOSFET control
    • Drives 3 high-side and 3 low-side N-channel MOSFETs (NMOS)
  • Smart gate drive architecture
    • Adjustable slew rate control
    • 1.5-mA to 1-A peak source current
    • 3-mA to 2-A peak sink current
  • Charge-pump of gate driver for 100% Duty Cycle
  • 3 Integrated current sense amplifiers (CSAs)
    • Adjustable gain (5, 10, 20, 40 V/V)
    • Bidirectional or unidirectional support
  • SPI (S) and hardware (H) interface available
  • 6x, 3x, 1x, and independent PWM modes
  • Supports 3.3-V, and 5-V logic inputs
  • Charge pump output can be used to drive the reverse supply protection MOSFET
  • Linear voltage regulator, 3.3 V, 30 mA
  • Integrated protection features
    • VM undervoltage lockout (UVLO)
    • Charge pump undervoltage (CPUV)
    • Short to battery (SHT_BAT)
    • Short to ground (SHT_GND)
    • MOSFET overcurrent protection (OCP)
    • Gate driver fault (GDF)
    • Thermal warning and shutdown (OTW/OTSD)
    • Fault condition indicator (nFAULT)
  • AEC-Q100 qualified for automotive applications
    • Temperature grade 1: –40°C ≤ TA ≤ 125°C
  • Three independent half-bridge gate driver
    • Dedicated source (SHx) and drain (DLx) pins to support independent MOSFET control
    • Drives 3 high-side and 3 low-side N-channel MOSFETs (NMOS)
  • Smart gate drive architecture
    • Adjustable slew rate control
    • 1.5-mA to 1-A peak source current
    • 3-mA to 2-A peak sink current
  • Charge-pump of gate driver for 100% Duty Cycle
  • 3 Integrated current sense amplifiers (CSAs)
    • Adjustable gain (5, 10, 20, 40 V/V)
    • Bidirectional or unidirectional support
  • SPI (S) and hardware (H) interface available
  • 6x, 3x, 1x, and independent PWM modes
  • Supports 3.3-V, and 5-V logic inputs
  • Charge pump output can be used to drive the reverse supply protection MOSFET
  • Linear voltage regulator, 3.3 V, 30 mA
  • Integrated protection features
    • VM undervoltage lockout (UVLO)
    • Charge pump undervoltage (CPUV)
    • Short to battery (SHT_BAT)
    • Short to ground (SHT_GND)
    • MOSFET overcurrent protection (OCP)
    • Gate driver fault (GDF)
    • Thermal warning and shutdown (OTW/OTSD)
    • Fault condition indicator (nFAULT)

The DRV8343-Q1 device is an integrated gate driver for three-phase applications. The device provides three half-bridge gate drivers, each capable of driving high-side and low-side N-channel power MOSFETs. The dedicated Source and Drain pins enable the independent MOSFET control for solenoid application. The DRV8343-Q1 generates the correct gate drive voltages using an integrated charge pump sufficient for the high-side MOSFETs and a linear regulator for the low-side MOSFETs. The Smart Gate Drive architecture supports peak gate drive currents up to 1-A source and 2-A. The DRV8343-Q1 can operate from a single power supply and supports a wide input supply range of 5.5 to 60 V for the gate driver.

The 6x, 3x, 1x, and independent input PWM modes allow for simple interfacing to controller circuits. The configuration settings for the gate driver and device are highly configurable through the SPI or hardware (H/W) interface. The DRV8343-Q1 device integrates three low-side current sense amplifiers that allow bidirectional current sensing on all three phases of the drive stage.

A low-power sleep mode is provided to achieve low quiescent current. Internal protection functions are provided for undervoltage lockout, charge pump fault, MOSFET overcurrent, MOSFET short circuit, phase-node short to supply and ground, gate driver fault, and overtemperature. Fault conditions are indicated on the nFAULT pin with details through the device registers for the SPI device variant.

The DRV8343-Q1 device is an integrated gate driver for three-phase applications. The device provides three half-bridge gate drivers, each capable of driving high-side and low-side N-channel power MOSFETs. The dedicated Source and Drain pins enable the independent MOSFET control for solenoid application. The DRV8343-Q1 generates the correct gate drive voltages using an integrated charge pump sufficient for the high-side MOSFETs and a linear regulator for the low-side MOSFETs. The Smart Gate Drive architecture supports peak gate drive currents up to 1-A source and 2-A. The DRV8343-Q1 can operate from a single power supply and supports a wide input supply range of 5.5 to 60 V for the gate driver.

The 6x, 3x, 1x, and independent input PWM modes allow for simple interfacing to controller circuits. The configuration settings for the gate driver and device are highly configurable through the SPI or hardware (H/W) interface. The DRV8343-Q1 device integrates three low-side current sense amplifiers that allow bidirectional current sensing on all three phases of the drive stage.

A low-power sleep mode is provided to achieve low quiescent current. Internal protection functions are provided for undervoltage lockout, charge pump fault, MOSFET overcurrent, MOSFET short circuit, phase-node short to supply and ground, gate driver fault, and overtemperature. Fault conditions are indicated on the nFAULT pin with details through the device registers for the SPI device variant.

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Technische Dokumentation

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Typ Titel Datum
* Data sheet DRV8343-Q1 12-V / 24-V Automotive Gate Driver Unit (GDU) with Independent Half Bridge Control and Three Integrated Current Sense Amplifiers datasheet (Rev. A) PDF | HTML 09 Apr 2019
Application note Using DRV to Drive Solenoids (Rev. A) PDF | HTML 24 Apr 2022
Application note Best Practices for Board Layout of Motor Drivers (Rev. B) PDF | HTML 14 Okt 2021
Application note Hardware Design Considerations for an Electric Bicycle using BLDC Motor (Rev. B) 23 Jun 2021
Application note System Design Considerations for High-Power Motor Driver Applications PDF | HTML 22 Jun 2021
Technical article A basic brushless gate driver design – part 3: integrated vs. discrete half bridge PDF | HTML 16 Dez 2020
Technical article How analog integration simplifies automotive body motor controller designs PDF | HTML 23 Okt 2020
Technical article How to efficiently drive 12-V and 24-V engine loads in automotive systems PDF | HTML 09 Jul 2020
Application note Switched Reluctance Motor (SRM) Inverter Design With the DRV8343-Q1 30 Jan 2020
EVM User's guide DRV8343H-Q1EVM and DRV8343S-Q1EVM User's Guide (Rev. B) 18 Apr 2019
Application note Protecting Automotive Motor Drive Systems from Reverse Polarity Conditions (Rev. A) 19 Feb 2019
User guide DRV8343x-Q1EVM GUI User's Guide 29 Jan 2018
EVM User's guide DRV8343x-Q1EVM Independent Mode User's Guide 29 Jan 2018
EVM User's guide DRV8343x-Q1EVM Sensored Software User's Guide 29 Jan 2018
EVM User's guide DRV8343x-Q1EVM Sensorless Software User's Guide 29 Jan 2018

Design und Entwicklung

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Evaluierungsplatine

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The DRV8343H-Q1EVM evaluation module is a 6V to 60V, 20A, a highly configurable 3-phase brushless DC (BLDC) motor drive and control evaluation platform designed for 12-V to 24-V automotive systems based on the DRV8343H-Q1 automotive smart gate driver.  The EVM has onboard reverse battery (...)
Benutzerhandbuch: PDF
Evaluierungsplatine

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Benutzerhandbuch: PDF
Simulationsmodell

DRV834XQ1 PSPICE Model

SLVMD44.ZIP (246 KB) - PSpice Model
Berechnungstool

BLDC-MAX-QG-MOSFET-CALCULATOR Calculate the maximum QG MOSFET for your motor driver

Calculate the maximum QG MOSFET that can be driven based on the PWM switching frequency, algorithm type, and additional external capacitance.
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Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
HTQFP (PHP) 48 Ultra Librarian

Bestellen & Qualität

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  • Blei-Finish/Ball-Material
  • MSL-Rating / Spitzenrückfluss
  • MTBF-/FIT-Schätzungen
  • Materialinhalt
  • Qualifikationszusammenfassung
  • Kontinuierliches Zuverlässigkeitsmonitoring
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