LMK04803
Rauscharmer Takt-Jitter-Cleaner mit zwei kaskadierten PLLs und integriertem 1,9-GHz-VCO
LMK04803
- Ultra-Low RMS Jitter Performance
- 111 fs RMS Jitter (12 kHz to 20 MHz)
- 123 fs RMS Jitter (100 Hz to 20 MHz)
- Dual Loop PLLatinum™ PLL Architecture
- PLL1
- Integrated Low-Noise Crystal Oscillator
Circuit - Holdover Mode when Input Clocks are Lost
- Automatic or Manual Triggering/Recovery
- Integrated Low-Noise Crystal Oscillator
- PLL2
- Normalized PLL Noise Floor of –227 dBc/Hz
- Phase Detector Rate up to 155 MHz
- OSCin Frequency-Doubler
- Integrated Low-Noise VCO
- 2 Redundant Input Clocks with LOS
- Automatic and Manual Switch-Over Modes
- 50 % Duty Cycle Output Divides, 1 to 1045 (Even
and Odd) - 12 LVPECL, LVDS, or LVCMOS Programmable
Outputs - Digital Delay: Fixed or Dynamically Adjustable
- 25 ps Step Analog Delay Control.
- 14 Differential Outputs. Up to 26 Single Ended.
- Up to 6 VCXO/Crystal Buffered Outputs
- Clock Rates of up to 1536 MHz
- 0-Delay Mode
- Three Default Clock Outputs at Power Up
- Multi-Mode: Dual PLL, Single PLL, and Clock
Distribution - Industrial Temperature Range: –40 to 85°C
- 3.15-V to 3.45-V Operation
- 2 Dedicated Buffered/Divided OSCin Clocks
- Package: 64-Pin WQFN (9.0 × 9.0 × 0.8 mm)
The LMK0480x family is the industrys highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum architecture is capable of 111 fs rms jitter (12 kHz to 20 MHz) using a low noise VCXO module or sub-200 fs rms jitter (12 kHz to 20 MHz) using a low cost external crystal and varactor diode.
The dual loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides low-noise jitter cleaner functionality while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When paired with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.
Ähnliche Produkte, die für Sie interessant sein könnten
Selbe Funktionalität wie der verglichene Baustein bei gleicher Anschlussbelegung
Technische Dokumentation
Typ | Titel | Datum | ||
---|---|---|---|---|
* | Data sheet | LMK0480x Low-Noise Clock Jitter Cleaner with Dual Loop PLLs datasheet (Rev. K) | PDF | HTML | 24 Dez 2014 |
Application note | Clocking for Medical Ultrasound Systems (Rev. A) | PDF | HTML | 30 Sep 2020 | |
User guide | TSW308x Evaluation Module (Rev. B) | 18 Mai 2016 | ||
EVM User's guide | TSW4806EVM User's Guide (Rev. A) | 26 Apr 2016 | ||
EVM User's guide | LMK0480x Evaluation Board Instructions (Rev. B) | 04 Aug 2014 | ||
Design guide | TSW1265 Dual-Wideband RF-to-Digital Receiver Design Guide | 03 Sep 2013 | ||
Application note | Using the LMK0480x/LMK04906 for Hitless Switching and Holdover | 12 Jul 2013 | ||
User guide | TSW3085EVM ACPR and EVM Measurements (TIDA-00076 Reference Guide) | 29 Dez 2011 | ||
Design guide | Clock Conditioner Owner's Manual | 10 Nov 2006 |
Design und Entwicklung
Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.
TSW1265EVM — Referenzdesign und Evaluierungsplattform für Breitband-Zweifach-Empfänger
The TSW1265EVM is a wideband dual receiver reference design and evaluation platform. The signal chain allows conversion from RF to bits using a dual-channel downconverter mixer, the LMH6521 dual-channel DVGA, and the ADS4249 14-bit 250-MSPS ADC. The TSW1265EVM also includes the LMK04800 dual-PLL (...)
TSW3084EVM — Evaluierungsplatine und Referenzdesign für Breitband-Übertragungssignalkette
The TSW3084EVM Evaluation Module is a circuit board that allows system designers to evaluate the combined performance of Texas Instruments' transmit signal chain with the LMK04806B low noise clock generator/jitter cleaner. For ease of use as a complete RF transmit solution the TSW3084EVM includes (...)
TSW30H84EVM — Evaluierungsplatine und Referenzdesign für Breitband-Übertragungssignalkette
The TSW30H84EVM Evaluation Module is a circuit board that allows system designers to evaluate the combined performance of Texas Instruments' transmit signal chain with the LMK04806B (Please see LMK04800) low noise clock generator/jitter cleaner. For ease of use as a complete RF transmit solution (...)
SLAC532 — TSW4806 Installer GUI
Unterstützte Produkte und Hardware
Produkte
Takt-Jitter-Cleaner
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
Unterstützte Produkte und Hardware
Produkte
Taktgeneratoren
Taktpuffer
Oscillators
Takt-Jitter-Cleaner
Netzwerk-Taktsynchronisierer
HF-PLLs und Synthesizer
Hardware-Entwicklung
Evaluierungsplatine
Software
IDE, Konfiguration, Compiler oder Debugger
CLOCK-TREE-ARCHITECT — Programmiersoftware Clock Tree Architect
PLLATINUMSIM-SW — PLLatinum Sim Tool
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
Unterstützte Produkte und Hardware
Produkte
Taktpuffer
Taktgeneratoren
Takt-Jitter-Cleaner
Netzwerk-Taktsynchronisierer
HF-PLLs und Synthesizer
IQ-Demodulatoren
Hardware-Entwicklung
Evaluierungsplatine
Software
Anwendungssoftware und Frameworks
IDE, Konfiguration, Compiler oder Debugger
Support-Software
PSPICE-FOR-TI — PSpice® für TI Design-und Simulationstool
TIDA-00074 — Breitbandige HF-Digital-Komplexempfänger-Feedback-Signalkette
Gehäuse | Pins | CAD-Symbole, Footprints und 3D-Modelle |
---|---|---|
WQFN (NKD) | 64 | Ultra Librarian |
Bestellen & Qualität
- RoHS
- REACH
- Bausteinkennzeichnung
- Blei-Finish/Ball-Material
- MSL-Rating / Spitzenrückfluss
- MTBF-/FIT-Schätzungen
- Materialinhalt
- Qualifikationszusammenfassung
- Kontinuierliches Zuverlässigkeitsmonitoring
- Werksstandort
- Montagestandort
Empfohlene Produkte können Parameter, Evaluierungsmodule oder Referenzdesigns zu diesem TI-Produkt beinhalten.
Support und Schulungen
TI E2E™-Foren mit technischem Support von TI-Ingenieuren
Inhalte werden ohne Gewähr von TI und der Community bereitgestellt. Sie stellen keine Spezifikationen von TI dar. Siehe Nutzungsbedingungen.
Bei Fragen zu den Themen Qualität, Gehäuse oder Bestellung von TI-Produkten siehe TI-Support.