SN74ABT162244

Name: SN74ABT162244
Brand: TI
SKU: SN74ABT162244
Price: 0.501 USD

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16-Kanal-Puffer, 4,5 V bis 5,5 V, mit TTL-kompatiblen CMOS-Eingängen und Tri-State-Ausgängen

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Datenblatt

document-pdfAcrobat SN54ABT162244, SN74ABT162244 datasheet (Rev. E) (Englisch)

SN74ABT162244

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Datenblatt

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Produktdetails

Technology family

ABT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Number of channels

16

IOL (max) (mA)

12

Supply current (max) (µA)

30000

IOH (max) (mA)

-12

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Balanced outputs, Damping resistors, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

ABT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Number of channels

16

IOL (max) (mA)

12

Supply current (max) (µA)

30000

IOH (max) (mA)

-12

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Balanced outputs, Damping resistors, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SSOP (DL)

48

164.358 mm² 15.88 x 10.35

TSSOP (DGG)

48

101.25 mm² 12.5 x 8.1

TVSOP (DGV)

48

62.08 mm² 9.7 x 6.4

Members of the Texas Instruments Widebus™ Family
Output Ports Have Equivalent 25- Series Resistors, So No External Resistors Are Required
Typical V_OLP (Output Ground Bounce) <1 V at V_CC = 5 V, T_A = 25°C
High-Impedance State During Power Up and Power Down
I_off and Power-Up 3-State Support Hot Insertion
Distributed V_CC and GND Pins Minimize High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB Layout
Latch-Up Performance Exceeds 500 mA Per JESD-17

Widebus is a trademark of Texas Instruments.

Members of the Texas Instruments Widebus™ Family
Output Ports Have Equivalent 25- Series Resistors, So No External Resistors Are Required
Typical V_OLP (Output Ground Bounce) <1 V at V_CC = 5 V, T_A = 25°C
High-Impedance State During Power Up and Power Down
I_off and Power-Up 3-State Support Hot Insertion
Distributed V_CC and GND Pins Minimize High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB Layout
Latch-Up Performance Exceeds 500 mA Per JESD-17

Widebus is a trademark of Texas Instruments.

The ’ABT162244 devices are 16-bit buffers and line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide noninverting outputs and symmetrical active-low output-enable (OE)\ inputs.

The outputs, which are designed to source or sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

The ’ABT162244 devices are 16-bit buffers and line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide noninverting outputs and symmetrical active-low output-enable (OE)\ inputs.

The outputs, which are designed to source or sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

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Alle anzeigen 19

	Typ	Titel	Datum
*	Data sheet	SN54ABT162244, SN74ABT162244 datasheet (Rev. E)	03 Jun 2004
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	26 Jul 2021
	Selection guide	Logic Guide (Rev. AB)	12 Jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 Dez 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 Jan 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 Jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)	22 Jun 2004
	Application note	Quad Flatpack No-Lead Logic Packages (Rev. D)	16 Feb 2004
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	29 Aug 2002
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices	10 Mai 2002
	Selection guide	Advanced Bus Interface Logic Selection Guide	09 Jan 2001
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)	01 Aug 1997
	Application note	Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B)	01 Jun 1997
	Application note	Designing With Logic (Rev. C)	01 Jun 1997
	Application note	Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A)	01 Mär 1997
	Application note	Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A)	01 Dez 1996
	Application note	Input and Output Characteristics of Digital Integrated Circuits	01 Okt 1996
	Application note	Live Insertion	01 Okt 1996
	Application note	Understanding Advanced Bus-Interface Products Design Guide	01 Mai 1996

Design und Entwicklung

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