SN74ABT16827

Name: SN74ABT16827
Brand: TI
SKU: SN74ABT16827
Price: 1.435 USD

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20-Kanal-Puffer, 4,5 V bis 5,5 V, mit TTL-kompatiblen CMOS-Eingängen und Tri-State-Ausgängen

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Datenblatt

document-pdfAcrobat 20-Bit Buffers/Drivers With 3-State Outputs datasheet (Rev. C) (Englisch)

SN74ABT16827

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Datenblatt

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Produktdetails

Technology family

ABT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Number of channels

20

IOL (max) (mA)

64

Supply current (max) (µA)

32000

IOH (max) (mA)

-32

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

ABT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Number of channels

20

IOL (max) (mA)

64

Supply current (max) (µA)

32000

IOH (max) (mA)

-32

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SSOP (DL)

56

190.647 mm² 18.42 x 10.35

Members of the Texas Instruments Widebus^TM Family
State-of-the-Art EPIC-II B^TM BiCMOS Design Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
Typical V_OLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C
High-Impedance State During Power Up and Power Down
Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB Layout
High-Drive Outputs (-32-mA I_OH, 64-mA I_OL)
Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Package and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
Widebus and EPIC-IIB are trademarks of Texas Instruments Incorporated.

Members of the Texas Instruments Widebus^TM Family
State-of-the-Art EPIC-II B^TM BiCMOS Design Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
Typical V_OLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C
High-Impedance State During Power Up and Power Down
Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB Layout
High-Drive Outputs (-32-mA I_OH, 64-mA I_OL)
Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Package and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
Widebus and EPIC-IIB are trademarks of Texas Instruments Incorporated.

The 'ABT16827 are noninverting 20-bit buffers composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer section, the two output-enable (1OE1\ and 1OE2\ or 2OE1\ and 2OE2\) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the high-impedance state.

When V_CC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16827 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16827 is characterized for operation from -40°C to 85°C.

The 'ABT16827 are noninverting 20-bit buffers composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer section, the two output-enable (1OE1\ and 1OE2\ or 2OE1\ and 2OE2\) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the high-impedance state.

When V_CC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16827 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16827 is characterized for operation from -40°C to 85°C.

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Alle anzeigen 19

	Typ	Titel	Datum
*	Data sheet	20-Bit Buffers/Drivers With 3-State Outputs datasheet (Rev. C)	01 Mai 1997
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	26 Jul 2021
	Selection guide	Logic Guide (Rev. AB)	12 Jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 Dez 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 Jan 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 Jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)	22 Jun 2004
	Application note	Quad Flatpack No-Lead Logic Packages (Rev. D)	16 Feb 2004
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	29 Aug 2002
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices	10 Mai 2002
	Selection guide	Advanced Bus Interface Logic Selection Guide	09 Jan 2001
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)	01 Aug 1997
	Application note	Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B)	01 Jun 1997
	Application note	Designing With Logic (Rev. C)	01 Jun 1997
	Application note	Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A)	01 Mär 1997
	Application note	Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A)	01 Dez 1996
	Application note	Input and Output Characteristics of Digital Integrated Circuits	01 Okt 1996
	Application note	Live Insertion	01 Okt 1996
	Application note	Understanding Advanced Bus-Interface Products Design Guide	01 Mai 1996

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