SN74ALVC16835

Name: SN74ALVC16835
Brand: TI
SKU: SN74ALVC16835
Price: 1.537 USD

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Universal-Bus-Treiber, 18 Bit, mit Tri-State-Ausgängen

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Datenblatt

document-pdfAcrobat SN74ALVC16835 datasheet (Rev. J) (Englisch)

SN74ALVC16835

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

3.6

Number of channels

18

IOL (max) (mA)

24

IOH (max) (mA)

-32

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Ultra high speed (tpd <5ns)

Technology family

ALVC

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

3.6

Number of channels

18

IOL (max) (mA)

24

IOH (max) (mA)

-32

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Ultra high speed (tpd <5ns)

Technology family

ALVC

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SSOP (DL)

56

190.647 mm² 18.42 x 10.35

TSSOP (DGG)

56

113.4 mm² 14 x 8.1

Member of the Texas Instruments Widebus™ Family
Operates From 1.65 V to 3.6 V
Max t_pd of 2 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Ideal for Use in PC100 Register DIMM Revision 1.1
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

Member of the Texas Instruments Widebus™ Family
Operates From 1.65 V to 3.6 V
Max t_pd of 2 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Ideal for Use in PC100 Register DIMM Revision 1.1
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

This 18-bit universal bus driver is designed for 1.65-V to 3.6-V V_CC operation.

Data flow from A to Y is controlled by the output-enable (OE)\ input. The device operates in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This 18-bit universal bus driver is designed for 1.65-V to 3.6-V V_CC operation.

Data flow from A to Y is controlled by the output-enable (OE)\ input. The device operates in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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Technische Dokumentation

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Alle anzeigen 18

	Typ	Titel	Datum
*	Data sheet	SN74ALVC16835 datasheet (Rev. J)	20 Okt 2004
	Selection guide	Logic Guide (Rev. AB)	12 Jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 Dez 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 Jan 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 Jul 2004
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	29 Aug 2002
	User guide	ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B)	01 Aug 2002
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards	13 Jun 2002
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)	22 Mai 2002
	Application note	Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)	08 Sep 1999
	Application note	TI SN74ALVC16835 Component Specification Analysis for PC100	03 Aug 1998
	Application note	Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)	13 Mai 1998
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices	01 Dez 1997
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)	01 Aug 1997
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	01 Jun 1997
	Application note	Input and Output Characteristics of Digital Integrated Circuits	01 Okt 1996
	Application note	Live Insertion	01 Okt 1996
	Application note	Understanding Advanced Bus-Interface Products Design Guide	01 Mai 1996

Design und Entwicklung

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Simulationsmodell

SN74ALVC16835 IBIS Model (Rev. A)

SCEM040A.ZIP (12 KB) - IBIS Model

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Gehäuse	Pins	CAD-Symbole, Footprints und 3D-Modelle
SSOP (DL)	56	Ultra Librarian
TSSOP (DGG)	56	Ultra Librarian

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SN74ALVC16835

Universal-Bus-Treiber, 18 Bit, mit Tri-State-Ausgängen

SN74ALVC16835

Produktdetails

Technische Dokumentation

Design und Entwicklung

SN74ALVC16835 IBIS Model (Rev. A)

Bestellen & Qualität

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