SN74ALVCH16524

Name: SN74ALVCH16524
Brand: TI
SKU: SN74ALVCH16524
Price: 4.784 USD

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Registrierte Bustransceiver, 18 Bit, mit Tri-State-Ausgängen

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Datenblatt

document-pdfAcrobat SN74ALVCH16524 datasheet (Rev. E) (Englisch)

SN74ALVCH16524

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Datenblatt

Jetzt bestellen

Produktdetails

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

3.6

Number of channels

18

IOL (max) (mA)

24

IOH (max) (mA)

-24

Input type

LVTTL

Output type

LVTTL

Features

Balanced outputs, Bus-hold, Ultra high speed (tpd <5ns)

Technology family

ALVC

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

3.6

Number of channels

18

IOL (max) (mA)

24

IOH (max) (mA)

-24

Input type

LVTTL

Output type

LVTTL

Features

Balanced outputs, Bus-hold, Ultra high speed (tpd <5ns)

Technology family

ALVC

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SSOP (DL)

56

190.647 mm² 18.42 x 10.35

Member of the Texas Instruments Widebus™ Family
UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enable Mode
Operates From 1.65-V to 3.6-V
Max t_pd of 3.2 ns at 3.3-V
±24-mA Output Drive at 3.3-V
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

Widebus, UBT are trademarks of Texas Instruments.

Member of the Texas Instruments Widebus™ Family
UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enable Mode
Operates From 1.65-V to 3.6-V
Max t_pd of 3.2 ns at 3.3-V
±24-mA Output Drive at 3.3-V
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

Widebus, UBT are trademarks of Texas Instruments.

This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V V_CC operation.

Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\) and clock-enable (CLKENBA\) inputs. For the A-to-B data flow, the data flows through a single buffer. The B-to-A data can flow through a four-stage pipeline register path, or through a single register path, depending on the state of the select (SEL\) input.

Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input, provided that the appropriate CLKENBA\ input is low. The B-to-A data transfer is synchronized with CLK.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V V_CC operation.

Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\) and clock-enable (CLKENBA\) inputs. For the A-to-B data flow, the data flows through a single buffer. The B-to-A data can flow through a four-stage pipeline register path, or through a single register path, depending on the state of the select (SEL\) input.

Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input, provided that the appropriate CLKENBA\ input is low. The B-to-A data transfer is synchronized with CLK.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

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Technische Dokumentation

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Alle anzeigen 18

	Typ	Titel	Datum
*	Data sheet	SN74ALVCH16524 datasheet (Rev. E)	01 Sep 2004
	Selection guide	Logic Guide (Rev. AB)	12 Jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 Dez 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 Jan 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 Jul 2004
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	29 Aug 2002
	User guide	ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B)	01 Aug 2002
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards	13 Jun 2002
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)	22 Mai 2002
	Application note	Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)	08 Sep 1999
	Application note	TI SN74ALVC16835 Component Specification Analysis for PC100	03 Aug 1998
	Application note	Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)	13 Mai 1998
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices	01 Dez 1997
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)	01 Aug 1997
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	01 Jun 1997
	Application note	Input and Output Characteristics of Digital Integrated Circuits	01 Okt 1996
	Application note	Live Insertion	01 Okt 1996
	Application note	Understanding Advanced Bus-Interface Products Design Guide	01 Mai 1996

Design und Entwicklung

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SSOP (DL)	56	Ultra Librarian

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SN74ALVCH16524

Registrierte Bustransceiver, 18 Bit, mit Tri-State-Ausgängen

SN74ALVCH16524

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Design und Entwicklung

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