SN74AVC16245

Name: SN74AVC16245
Brand: TI
SKU: SN74AVC16245
Price: 1.739 USD

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Bustransceiver, 16 Bit, mit Tri-State-Ausgängen

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Datenblatt

document-pdfAcrobat 16-Bit Bus Transceiver With 3-State Outputs datasheet (Rev. L) (Englisch)

SN74AVC16245

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Datenblatt

Jetzt bestellen

Produktdetails

Supply voltage (min) (V)

1.2

Supply voltage (max) (V)

3.6

Number of channels

16

IOL (max) (mA)

12

IOH (max) (mA)

-12

Input type

CMOS

Output type

CMOS

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Technology family

AVC

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Supply voltage (min) (V)

1.2

Supply voltage (max) (V)

3.6

Number of channels

16

IOL (max) (mA)

12

IOH (max) (mA)

-12

Input type

CMOS

Output type

CMOS

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Technology family

AVC

Rating

Catalog

Operating temperature range (°C)

-40 to 85

TSSOP (DGG)

48

101.25 mm² 12.5 x 8.1

TVSOP (DGV)

48

62.08 mm² 9.7 x 6.4

Member of the Texas Instruments Widebus^TM Family
EPIC^TM (Enhanced-Performance Implanted CMOS) Submicron Process
DOC^TM (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation
Less Than 2-ns Maximum Propagation Delay at 2.5-V and 3.3-V V_CC
Dynamic Drive Capability Is Equivalent to Standard Outputs With I_OH and I_OL of ±24 mA at 2.5-V V_CC
Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
I_off Supports Partial-Power-Down Mode Operation
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
Latch-Up Performance Exceeds 250 mA Per JESD 78
Package Options Include Plastic Thin Shrink Small-Outline (DGG) and Thin Very Small-Outline (DGV) Packages
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.

Member of the Texas Instruments Widebus^TM Family
EPIC^TM (Enhanced-Performance Implanted CMOS) Submicron Process
DOC^TM (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation
Less Than 2-ns Maximum Propagation Delay at 2.5-V and 3.3-V V_CC
Dynamic Drive Capability Is Equivalent to Standard Outputs With I_OH and I_OL of ±24 mA at 2.5-V V_CC
Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
I_off Supports Partial-Power-Down Mode Operation
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
Latch-Up Performance Exceeds 250 mA Per JESD 78
Package Options Include Plastic Thin Shrink Small-Outline (DGG) and Thin Very Small-Outline (DGV) Packages
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.

A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical V_OL vs I_OL and V_OH vs I_OH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC^TM) Circuitry Technology and Applications, literature number SCEA009.

This 16-bit (dual octal) noninverting bus transceiver is operational at 1.2-V to 3.6-V V_CC, but is designed specifically for 1.65-V to 3.6-V V_CC operation.

The SN74AVC16245 is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements.

This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE\) input can be used to disable the device so that the buses are effectively isolated.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74AVC16245 is characterized for operation from -40°C to 85°C.

A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical V_OL vs I_OL and V_OH vs I_OH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC^TM) Circuitry Technology and Applications, literature number SCEA009.

This 16-bit (dual octal) noninverting bus transceiver is operational at 1.2-V to 3.6-V V_CC, but is designed specifically for 1.65-V to 3.6-V V_CC operation.

The SN74AVC16245 is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements.

This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE\) input can be used to disable the device so that the buses are effectively isolated.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74AVC16245 is characterized for operation from -40°C to 85°C.

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Alle anzeigen 13

	Typ	Titel	Datum
*	Data sheet	16-Bit Bus Transceiver With 3-State Outputs datasheet (Rev. L)	21 Feb 2000
	Selection guide	Logic Guide (Rev. AB)	12 Jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 Dez 2015
	Application note	Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B)	30 Apr 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 Jan 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 Jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)	22 Jun 2004
	More literature	LCD Module Interface Application Clip	09 Mai 2003
	User guide	AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C)	20 Aug 2002
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards	13 Jun 2002
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)	22 Mai 2002
	Application note	Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B)	07 Jul 1999
	Application note	AVC Logic Family Technology and Applications (Rev. A)	26 Aug 1998

Design und Entwicklung

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