SN74LVCH16240A

Name: SN74LVCH16240A
Brand: TI
SKU: SN74LVCH16240A
Price: 0.432 USD

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16-Kanal-Wechselrichter, 2 bis 3,6 V, mit Bus-Hold und Tri-State-Ausgängen

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Datenblatt

document-pdfAcrobat 16-Bit Buffer/Driver With 3-State Outputs datasheet (Rev. H) (Englisch)

SN74LVCH16240A

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Technology family

LVC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

3.6

Number of channels

16

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

20

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Bus-hold, Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

LVC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

3.6

Number of channels

16

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

20

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Bus-hold, Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SSOP (DL)

48

164.358 mm² 15.88 x 10.35

TSSOP (DGG)

48

101.25 mm² 12.5 x 8.1

Member of the Texas Instruments Widebus™ Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t_pd of 4.2 ns at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Partial-Power-Down Mode Operation
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V V_CC)
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

Member of the Texas Instruments Widebus™ Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t_pd of 4.2 ns at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Partial-Power-Down Mode Operation
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V V_CC)
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

This 16-bit buffer/driver is designed for 1.65-V to 3.6-V V_CC operation.

The SN74LVCH16240A is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. This device provides inverting outputs and symmetrical active-low output-enable (OE)\ inputs.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This 16-bit buffer/driver is designed for 1.65-V to 3.6-V V_CC operation.

The SN74LVCH16240A is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. This device provides inverting outputs and symmetrical active-low output-enable (OE)\ inputs.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Alle anzeigen 28

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	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices	01 Dez 1997
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	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	01 Jun 1997
	Application note	LVC Characterization Information	01 Dez 1996
	Application note	Input and Output Characteristics of Digital Integrated Circuits	01 Okt 1996
	Application note	Live Insertion	01 Okt 1996
	Design guide	Low-Voltage Logic (LVC) Designer's Guide	01 Sep 1996
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Design und Entwicklung

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