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This 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.
All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are SSTL_2, Class II compatible.
The SN74SSTV16859 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low.
The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up.
| Typ | Titel | Datum | ||
|---|---|---|---|---|
| * | Data sheet | SN74SSTV16859 datasheet (Rev. D) | 03 Aug 2004 | |
| Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dez 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | ||
| Application note | 56-Pin Quad Flatpack No-Lead Logic Package | 07 Feb 2003 | ||
| Application note | Application of the SN74SSTVF16857 in Planar PC2700 (DDR-333) RDIMMs | 10 Jan 2003 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 Aug 2002 | ||
| More literature | DIMM Module Solution | 13 Jun 2002 | ||
| More literature | Standard Linear & Logic for PCs, Servers & Motherboards | 13 Jun 2002 | ||
| Application note | Application of the SN74SSTV32852 in Stacked, Low-Profile (1U) PC-1600/2100 DIMMs | 07 Nov 2001 | ||
| Application note | Low-Power Support Using Texas Instruments SN74SSTV16857 and SN74SSTV16859 | 09 Feb 2001 |
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