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CDCL1810

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Búfer de reloj diferencial de alto rendimiento de 1 a 10 de 1,8 V.

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CDCL1810

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Detalles del producto

Function Differential Additive RMS jitter (typ) (fs) 40 Output frequency (max) (MHz) 650 Number of outputs 10 Output supply voltage (V) 1.8 Core supply voltage (V) 1.8 Output skew (ps) 64 Features I2C interface Operating temperature range (°C) -40 to 85 Rating Catalog Output type CML Input type LVDS
Function Differential Additive RMS jitter (typ) (fs) 40 Output frequency (max) (MHz) 650 Number of outputs 10 Output supply voltage (V) 1.8 Core supply voltage (V) 1.8 Output skew (ps) 64 Features I2C interface Operating temperature range (°C) -40 to 85 Rating Catalog Output type CML Input type LVDS
VQFN (RGZ) 48 49 mm² 7 x 7
  • Single 1.8-V Supply
  • High-Performance Clock Distributor with
    10 Outputs
  • Low Input-to-Output Additive Jitter:
    as Low as 10fs RMS
  • Output Group Phase Adjustment
  • Low-Voltage Differential Signaling (LVDS)
    Input, 100-Ω Differential On-Chip
    Termination, up to 650 MHz Frequency
  • Differential Current Mode Logic (CML)
    Outputs, 50-Ω Single-Ended On-Chip
    Termination, up to 650 MHz Frequency
  • Two Groups of Five Outputs Each with
    Independent Frequency Division Ratios
  • Output Frequency Derived with Divide
    Ratios of 1, 2, 4, 5, 8, 10, 16, 20,
    32, 40, and 80
  • Meets ANSI TIA/EIA-644-A-2001 LVDS
    Standard Requirements
  • Power Consumption: 410 mW Typical
  • Output Enable Control for Each Output
    and Automatic Output Synchronization
  • SDA/SCL Device Management Interface
  • 48-pin VQFN (RGZ) Package
  • Industrial Temperature Range:
    –40°C to +85°C
  • Single 1.8-V Supply
  • High-Performance Clock Distributor with
    10 Outputs
  • Low Input-to-Output Additive Jitter:
    as Low as 10fs RMS
  • Output Group Phase Adjustment
  • Low-Voltage Differential Signaling (LVDS)
    Input, 100-Ω Differential On-Chip
    Termination, up to 650 MHz Frequency
  • Differential Current Mode Logic (CML)
    Outputs, 50-Ω Single-Ended On-Chip
    Termination, up to 650 MHz Frequency
  • Two Groups of Five Outputs Each with
    Independent Frequency Division Ratios
  • Output Frequency Derived with Divide
    Ratios of 1, 2, 4, 5, 8, 10, 16, 20,
    32, 40, and 80
  • Meets ANSI TIA/EIA-644-A-2001 LVDS
    Standard Requirements
  • Power Consumption: 410 mW Typical
  • Output Enable Control for Each Output
    and Automatic Output Synchronization
  • SDA/SCL Device Management Interface
  • 48-pin VQFN (RGZ) Package
  • Industrial Temperature Range:
    –40°C to +85°C

The CDCL1810 is a high-performance clock distributor. The programmable dividers, P0 and P1, give a high flexibility to the ratio of the output frequency to the input frequency: FOUT = FIN/P, where: P (P0,P1) = 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, 80.

The CDCL1810 supports one differential LVDS clock input and a total of 10 differential CML outputs. The CML outputs are compatible with LVDS receivers if they are ac-coupled.

With careful observation of the input voltage swing and common-mode voltage limits, the CDCL1810 can support a single-ended clock input as outlined in Pin Configuration and Functions.

All device settings are programmable through the SDA/SCL, serial two-wire interface. The serial interface is 1.8V tolerant only.

The phase of one output group relative to the other can be adjusted through the SDA/SCL interface. For post-divide ratios (P0, P1) that are multiples of 5, the total number of phase adjustment steps (η) equals the divide-ratio divided by 5. For post-divide ratios (P0, P1) that are not multiples of 5, the total number of steps (η) is the same as the post-divide ratio. The phase adjustment step (ΔΦ) in time units is given as: ΔΦ = 1/(n × FOUT), where FOUT is the respective output frequency.

The device operates in a 1.8-V supply environment and is characterized for operation from –40°C to +85°C. The CDCL1810 is available in a 48-pin VQFN (RGZ) package.

The CDCL1810 is a high-performance clock distributor. The programmable dividers, P0 and P1, give a high flexibility to the ratio of the output frequency to the input frequency: FOUT = FIN/P, where: P (P0,P1) = 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, 80.

The CDCL1810 supports one differential LVDS clock input and a total of 10 differential CML outputs. The CML outputs are compatible with LVDS receivers if they are ac-coupled.

With careful observation of the input voltage swing and common-mode voltage limits, the CDCL1810 can support a single-ended clock input as outlined in Pin Configuration and Functions.

All device settings are programmable through the SDA/SCL, serial two-wire interface. The serial interface is 1.8V tolerant only.

The phase of one output group relative to the other can be adjusted through the SDA/SCL interface. For post-divide ratios (P0, P1) that are multiples of 5, the total number of phase adjustment steps (η) equals the divide-ratio divided by 5. For post-divide ratios (P0, P1) that are not multiples of 5, the total number of steps (η) is the same as the post-divide ratio. The phase adjustment step (ΔΦ) in time units is given as: ΔΦ = 1/(n × FOUT), where FOUT is the respective output frequency.

The device operates in a 1.8-V supply environment and is characterized for operation from –40°C to +85°C. The CDCL1810 is available in a 48-pin VQFN (RGZ) package.
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* Data sheet CDCL1810 1.8-V, 10 Output, High-Performance Clock Distributor datasheet (Rev. D) PDF | HTML 10 nov 2014

Diseño y desarrollo

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Modelo de simulación

CDCL1810 IBIS Model

SLLC321.ZIP (23 KB) - IBIS Model
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Modelo de simulación

CDCL1810A IBIS Software

SNAC065.ZIP (23 KB) - IBIS Model
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