CDCM1802

Name: CDCM1802
Brand: TI
SKU: CDCM1802
Price: 4.778 USD

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Búfer de reloj con divisor programable, E/S LVPECL y salida LVCMOS

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document-pdfAcrobat CDCM1802 Clock Buffer With Programmable Divider, LVPECL I/O + Additional LVCMOS Output datasheet (Rev. C) (Inglés) PDF | HTML

CDCM1802

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Detalles del producto

Function

Clock divider, Fanout

Additive RMS jitter (typ) (fs)

150

Output frequency (max) (MHz)

800

Number of outputs

1

Output supply voltage (V)

3.3

Core supply voltage (V)

3.3

Output skew (ps)

1600

Features

Pin programmable

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVCMOS, LVPECL

Input type

LVPECL

Function

Clock divider, Fanout

Additive RMS jitter (typ) (fs)

150

Output frequency (max) (MHz)

800

Number of outputs

1

Output supply voltage (V)

3.3

Core supply voltage (V)

3.3

Output skew (ps)

1600

Features

Pin programmable

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVCMOS, LVPECL

Input type

LVPECL

VQFN (RGT)

16

9 mm² 3 x 3

Distributes One Differential Clock Input to One LVPECL Differential Clock Output and One LVCMOS Single-Ended Output
Programmable Output Divider for Both LVPECL and LVCMOS Outputs
1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise
3.3-V Power Supply (2.5-V Functional)
Signaling Rate Up to 800-MHz LVPECL and
200-MHz LVCMOS
Differential Input Stage for Wide Common-Mode Range Also Provides VBB Bias Voltage Output for Single-Ended Input Signals
Receiver Input Threshold ±75 mV
16-Pin VQFN Package (3.00 mm × 3.00 mm)

Distributes One Differential Clock Input to One LVPECL Differential Clock Output and One LVCMOS Single-Ended Output
Programmable Output Divider for Both LVPECL and LVCMOS Outputs
1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise
3.3-V Power Supply (2.5-V Functional)
Signaling Rate Up to 800-MHz LVPECL and
200-MHz LVCMOS
Differential Input Stage for Wide Common-Mode Range Also Provides VBB Bias Voltage Output for Single-Ended Input Signals
Receiver Input Threshold ±75 mV
16-Pin VQFN Package (3.00 mm × 3.00 mm)

The CDCM1802 clock driver distributes one pair of differential clock input to one LVPECL differential clock output pair, Y0 and Y0, and one single-ended LVCMOS output, Y1. It is specifically designed for driving 50-Ω transmission lines. The LVCMOS output is delayed by 1.6 ns over the PECL output stage to minimize noise impact during signal transitions.

The CDCM1802 has two control pins, S0 and S1, to select different output mode settings. The S[1:0] pins are 3-level inputs. Additionally, an enable pin EN is provided to disable or enable all outputs simultaneously. The CDCM1802 is characterized for operation from −40°C to 85°C.

For single-ended driver applications, the CDCM1802 provides a VBB output pin that can be directly connected to the unused input as a common-mode voltage reference.

The CDCM1802 clock driver distributes one pair of differential clock input to one LVPECL differential clock output pair, Y0 and Y0, and one single-ended LVCMOS output, Y1. It is specifically designed for driving 50-Ω transmission lines. The LVCMOS output is delayed by 1.6 ns over the PECL output stage to minimize noise impact during signal transitions.

The CDCM1802 has two control pins, S0 and S1, to select different output mode settings. The S[1:0] pins are 3-level inputs. Additionally, an enable pin EN is provided to disable or enable all outputs simultaneously. The CDCM1802 is characterized for operation from −40°C to 85°C.

For single-ended driver applications, the CDCM1802 provides a VBB output pin that can be directly connected to the unused input as a common-mode voltage reference.

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Documentación técnica

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	Tipo	Título		Fecha
*	Data sheet	CDCM1802 Clock Buffer With Programmable Divider, LVPECL I/O + Additional LVCMOS Output datasheet (Rev. C)	PDF \| HTML	06 jul 2017
	Application note	CDCM1802/CDCM1804		04 ago 2004

Diseño y desarrollo

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Modelo de simulación

CDCM1802 IBIS Model

SCAC051.ZIP (25 KB) - IBIS Model

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)

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Encapsulado	Pines	Símbolos CAD, huellas y modelos 3D
VQFN (RGT)	16	Ultra Librarian

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CDCM1802

Búfer de reloj con divisor programable, E/S LVPECL y salida LVCMOS

CDCM1802

Detalles del producto

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Funcionalidad similar a la del dispositivo comparado

Documentación técnica

Diseño y desarrollo

CDCM1802 IBIS Model

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

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Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

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