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SN74SSTVF16859

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Búfer registrado de 13 bits a 26 bits de 500 MHz con entradas y salidas SSTL_2

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SN74SSTVF16859

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Detalles del producto

Function Memory interface Output frequency (max) (MHz) 500 Number of outputs 26 Output supply voltage (V) 2.5 Core supply voltage (V) 2.5 Features DDR register Operating temperature range (°C) 0 to 70 Rating Military Output type SSTL-18 Input type SSTL-18
Function Memory interface Output frequency (max) (MHz) 500 Number of outputs 26 Output supply voltage (V) 2.5 Core supply voltage (V) 2.5 Features DDR register Operating temperature range (°C) 0 to 70 Rating Military Output type SSTL-18 Input type SSTL-18
TSSOP (DGG) 64 137.7 mm² 17 x 8.1 VQFNP (RGQ) 56 64 mm² 8 x 8
  • Member of the Texas Instruments Widebus™ Family
  • Operates at 2.3 V to 2.7 V for PC1600, PC2100, and PC2700
  • Operates at 2.5 V to 2.7 V for PC3200 (QFN Package)
  • Pinout and Functionality Compatible With JEDEC Standard SSTV16859
  • 600 ps Faster (Simultaneous Switching) Than the JEDEC Standard SSTV16859 in PC2700 DIMM Applications
  • 1-to-2 Outputs to Support Stacked DDR DIMMs
  • Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line
  • Outputs Meet SSTL_2 Class I Specifications
  • Supports SSTL_2 Data Inputs
  • Differential Clock (CLK and CLK\) Inputs
  • Supports LVCMOS Switching Levels on the RESET\ Input
  • RESET\ Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low
  • Pinout Optimizes DIMM PCB Layout
  • Latch-Up Performance Exceeds 100mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.
  • Member of the Texas Instruments Widebus™ Family
  • Operates at 2.3 V to 2.7 V for PC1600, PC2100, and PC2700
  • Operates at 2.5 V to 2.7 V for PC3200 (QFN Package)
  • Pinout and Functionality Compatible With JEDEC Standard SSTV16859
  • 600 ps Faster (Simultaneous Switching) Than the JEDEC Standard SSTV16859 in PC2700 DIMM Applications
  • 1-to-2 Outputs to Support Stacked DDR DIMMs
  • Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line
  • Outputs Meet SSTL_2 Class I Specifications
  • Supports SSTL_2 Data Inputs
  • Differential Clock (CLK and CLK\) Inputs
  • Supports LVCMOS Switching Levels on the RESET\ Input
  • RESET\ Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low
  • Pinout Optimizes DIMM PCB Layout
  • Latch-Up Performance Exceeds 100mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

This 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.

All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are edge-controlled LVCMOS circuits optimized for unterminated DIMM loads.

The SN74SSTVF16859 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low.

The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up.

This 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.

All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are edge-controlled LVCMOS circuits optimized for unterminated DIMM loads.

The SN74SSTVF16859 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low.

The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up.
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Documentación técnica

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Tipo Título Fecha
* Data sheet SN74SSTVF16859 datasheet (Rev. B) 30 ene 2004
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note 56-Pin Quad Flatpack No-Lead Logic Package 07 feb 2003
Application note Application of the SN74SSTVF16857 in Planar PC2700 (DDR-333) RDIMMs 10 ene 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
More literature DIMM Module Solution 13 jun 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 jun 2002
Application note Application of the SN74SSTV32852 in Stacked, Low-Profile (1U) PC-1600/2100 DIMMs 07 nov 2001
Application note Low-Power Support Using Texas Instruments SN74SSTV16857 and SN74SSTV16859 09 feb 2001

Diseño y desarrollo

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Modelo de simulación

HSPICE Model of SN74SSTVF16859 (Rev. A)

SCEJ145A.ZIP (48 KB) - HSpice Model
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Modelo de simulación

SN74SSTVF16859DGG IBIS Model

SCEM341.ZIP (18 KB) - IBIS Model
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Modelo de simulación

SN74SSTVF16859RGQ IBIS Model

SCEM342.ZIP (18 KB) - IBIS Model
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Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TSSOP (DGG) 64 Ultra Librarian
VQFNP (RGQ) 56 Ultra Librarian
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Pedidos y calidad

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  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
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  • Resumen de calificaciones
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