Detalles del producto

Configuration 1:1 SPST Number of channels 3 Power supply voltage - single (V) 0.8, 1.2, 1.8, 2.5, 3.3, 5 Protocols Analog Ron (typ) (Ω) 3.5 CON (typ) (pF) 10.5 ON-state leakage current (max) (µA) 5 Supply current (typ) (µA) 0.07 Bandwidth (MHz) 100 Operating temperature range (°C) -40 to 85 Input/output continuous current (max) (mA) 64 Rating Catalog Drain supply voltage (max) (V) 5 Supply voltage (max) (V) 5
Configuration 1:1 SPST Number of channels 3 Power supply voltage - single (V) 0.8, 1.2, 1.8, 2.5, 3.3, 5 Protocols Analog Ron (typ) (Ω) 3.5 CON (typ) (pF) 10.5 ON-state leakage current (max) (µA) 5 Supply current (typ) (µA) 0.07 Bandwidth (MHz) 100 Operating temperature range (°C) -40 to 85 Input/output continuous current (max) (mA) 64 Rating Catalog Drain supply voltage (max) (V) 5 Supply voltage (max) (V) 5
SSOP (DCT) 8 11.8 mm² 2.95 x 4 VSSOP (DCU) 8 6.2 mm² 2 x 3.1
  • Designed to be used in voltage-limiting applications
  • 3.5-ω on-state connection between ports A and B
  • Flow-through pinout for ease of printed circuit board trace routing
  • Direct interface with GTL+ levels
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22:
    • 2000-V Human-Body Model
    • 200-V Machine Model
    • 1000-V Charged-Device Model
  • Designed to be used in voltage-limiting applications
  • 3.5-ω on-state connection between ports A and B
  • Flow-through pinout for ease of printed circuit board trace routing
  • Direct interface with GTL+ levels
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22:
    • 2000-V Human-Body Model
    • 200-V Machine Model
    • 1000-V Charged-Device Model

The SN74TVC3306 device provides three parallel NMOS pass transistors with a common unbuffered gate. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The device can be used as a dual switch, with the gates cascaded together to a reference transistor. The low-voltage side of each pass transistor is limited to a voltage set by the reference transistor. This is done to protect components with inputs that are sensitive to high-state voltage-level overshoots.

The SN74TVC3306 device provides three parallel NMOS pass transistors with a common unbuffered gate. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The device can be used as a dual switch, with the gates cascaded together to a reference transistor. The low-voltage side of each pass transistor is limited to a voltage set by the reference transistor. This is done to protect components with inputs that are sensitive to high-state voltage-level overshoots.

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Documentación técnica

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Tipo Título Fecha
* Data sheet SN74TVC3306 Dual Voltage Clamp datasheet (Rev. E) PDF | HTML 05 sep 2023
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 02 jun 2022
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 01 dic 2021
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 jun 2004
User guide Signal Switch Data Book (Rev. A) 14 nov 2003
More literature I2C and Serial Bus Devices Application Clip 10 jul 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 jun 2002

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

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Guía del usuario: PDF
Adaptador de interfaz

LEADED-ADAPTER1 — Adaptador de montaje superficial a conector macho DIP para pruebas rápidas de encapsulados con plomo

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

Guía del usuario: PDF
Modelo de simulación

HSPICE Model of SN74TVC3306

SCEJ172.ZIP (81 KB) - HSpice Model
Modelo de simulación

SN74TVC3306 IBIS Model (Rev. A)

SCDM002A.ZIP (35 KB) - IBIS Model
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SSOP (DCT) 8 Ultra Librarian
VSSOP (DCU) 8 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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