Detalles del producto

Function General-purpose timer Iq (typ) (mA) 0.18 Rating Automotive Operating temperature range (°C) -40 to 125 Supply voltage (max) (V) 15 Supply voltage (min) (V) 2 TI functional safety category Functional Safety-Capable
Function General-purpose timer Iq (typ) (mA) 0.18 Rating Automotive Operating temperature range (°C) -40 to 125 Supply voltage (max) (V) 15 Supply voltage (min) (V) 2 TI functional safety category Functional Safety-Capable
SOIC (D) 8 29.4 mm² 4.9 x 6
  • AEC-Q100 qualified for automotive applications:
    • Temperature grade 1: –40°C to +125°C, TA
  • Functional Safety-Capable
  • Very-low power consumption
    • 1mW (typical) at VDD = 5V
  • Capable of operation in astable mode
  • CMOS output capable of swinging rail to rail
  • High-output-current capability
    • Sink 100mA (typical)
    • Source 10mA (typical)
  • Output fully compatible with CMOS, TTL, and MOS
  • Low supply current reduces spikes during output transitions
  • Single-supply operation from 2V to 15V
  • Temperature range: –40°C to +125°C
  • Functionally interchangeable with the NE555; has same pinout
  • AEC-Q100 qualified for automotive applications:
    • Temperature grade 1: –40°C to +125°C, TA
  • Functional Safety-Capable
  • Very-low power consumption
    • 1mW (typical) at VDD = 5V
  • Capable of operation in astable mode
  • CMOS output capable of swinging rail to rail
  • High-output-current capability
    • Sink 100mA (typical)
    • Source 10mA (typical)
  • Output fully compatible with CMOS, TTL, and MOS
  • Low supply current reduces spikes during output transitions
  • Single-supply operation from 2V to 15V
  • Temperature range: –40°C to +125°C
  • Functionally interchangeable with the NE555; has same pinout

The TLC555-Q1 is a monolithic timing circuit fabricated using TI LinCMOS™ technology. The timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2MHz. As a result of the high input impedance, this device supports smaller timing capacitors than capacitors used by the NE555. Thus, more accurate time delays and oscillations are possible. Power consumption is low across the full power-supply voltage range.

Like the NE555, the TLC555-Q1 has a trigger level equal to approximately one-third of the supply voltage, and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by using the control voltage pin (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set, and the output goes high. If TRIG is greater than the trigger level and the threshold input (THRES) is greater than the threshold level, the flip-flop is reset and the output goes low. The reset input (RESET) can override all other inputs and is used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output goes low. Whenever the output is low, a low-impedance path is provided between the discharge pin (DISCH) and GND. Tie all unused inputs to an appropriate logic level to prevent false triggering.

The TLC555-Q1 is a monolithic timing circuit fabricated using TI LinCMOS™ technology. The timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2MHz. As a result of the high input impedance, this device supports smaller timing capacitors than capacitors used by the NE555. Thus, more accurate time delays and oscillations are possible. Power consumption is low across the full power-supply voltage range.

Like the NE555, the TLC555-Q1 has a trigger level equal to approximately one-third of the supply voltage, and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by using the control voltage pin (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set, and the output goes high. If TRIG is greater than the trigger level and the threshold input (THRES) is greater than the threshold level, the flip-flop is reset and the output goes low. The reset input (RESET) can override all other inputs and is used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output goes low. Whenever the output is low, a low-impedance path is provided between the discharge pin (DISCH) and GND. Tie all unused inputs to an appropriate logic level to prevent false triggering.

Descargar Ver vídeo con transcripción Video

Productos similares que pueden interesarle

open-in-new Comparar alternativas
Pin por pin con la misma funcionalidad que el dispositivo comparado
TLC555 ACTIVO Temporizador de baja potencia de 2.1 MHz y 250 µA Industrial version with similar specifications.

Documentación técnica

star =Principal documentación para este producto seleccionada por TI
No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.
Ver todo 5
Tipo Título Fecha
* Data sheet TLC555-Q1 Automotive LinCMOS™ Technology Timer datasheet (Rev. C) PDF | HTML 17 abr 2024
Functional safety information TLC555-Q1 Functional Safety, FIT Rate, Failure Mode Distribution and Pin FMA (Rev. A) PDF | HTML 13 mar 2023
Technical article Power Tips: Multiply your output voltage PDF | HTML 20 jul 2016
Design guide EMC Compatible Automotive LED Rear Lamp Sequential-Turn Animation Design Guide 02 jun 2016
Application note TLC555-Q1 Used as a Positive and Negative Charge Pump 25 may 2016

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Modelo de simulación

TLC555 TINA-TI Astable Reference Design (Rev. B)

SLFM002B.TSC (100 KB) - TINA-TI Reference Design
Modelo de simulación

TLC555 TINA-TI Mono Reference Design (Rev. B)

SLFM003B.TSC (102 KB) - TINA-TI Reference Design
Modelo de simulación

TLC555 TINA-TI Spice Model

SLFM005.ZIP (9 KB) - TINA-TI Spice Model
Modelo de simulación

TLC555x and TLC556x PSpice Model (Rev. E)

SLFJ002E.ZIP (25 KB) - PSpice Model
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Diseños de referencia

PMP31073 — Diseño de referencia de convertidor elevador intercalado de seis fases y 1.44 kW

This reference design showcases an interleaved boost converter controlled by LM5122-Q1, operating from a 9.0-V to 16.0-V input voltage range, generating an output voltage of 24.0 V with a maximum load current of 60.0 A (10.0 A per phase).
Test report: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SOIC (D) 8 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Los productos recomendados pueden tener parámetros, módulos de evaluación o diseños de referencia relacionados con este producto de TI.

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

Si tiene preguntas sobre la calidad, el paquete o el pedido de productos de TI, consulte el soporte de TI. ​​​​​​​​​​​​​​

Videos