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TPIC6B273
- Low rDS(on)...5 Typical
- Avalanche Energy ...30 mJ
- Eight Power DMOS-Transistor Outputs of
150-mA Continuous Current - 500-mA Typical Current-Limiting Capability
- Output Clamp Voltage...50 V
- Low Power Consumption
The TPIC6B273 is a monolithic, high-voltage, medium-current, power logic octal D-type latch with DMOS-transistor outputs designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium-current or high-voltage loads.
The TPIC6B273 contains eight positive-edge-
triggered D-type flip-flops with a direct clear input. Each flip-flop features an open-drain power DMOS-transistor output.
When clear (CLR\) is high, information at the D inputs meeting the setup time requirements is transferred to the DRAIN outputs on the positive-
going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input (CLK) is at either the high or low level, the D input signal has no effect at the output. An asynchronous CLR\ is provided to turn all eight DMOS-transistor outputs off. When data is low for a given output, the DMOS-transistor output is off. When data is high, the DMOS-transistor output has sink-current capability.
Outputs are low-side, open-drain DMOS
transistors with output ratings of 50 V and 150-mA continuous sink-current capability. Each output provides a 500-mA typical current limit at
TC = 25°C. The current limit decreases as the junction temperature increases for additional device protection.
The TPIC6B273 is characterized for operation over the operating case temperature range of -40°C to 125°C.
技術資料
種類 | タイトル | 最新の英語版をダウンロード | 日付 | |||
---|---|---|---|---|---|---|
* | データシート | Power Logic Octal D-Type Latch データシート | 1995年 7月 1日 |
設計および開発
その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。
PSPICE-FOR-TI — TI Design / シミュレーション・ツール向け PSpice®
設計とシミュレーション向けの環境である PSpice for TI (...)
パッケージ | ピン数 | CAD シンボル、フットプリント、および 3D モデル |
---|---|---|
PDIP (N) | 20 | Ultra Librarian |
SOIC (DW) | 20 | Ultra Librarian |
購入と品質
- RoHS
- REACH
- デバイスのマーキング
- リード端子の仕上げ / ボールの原材料
- MSL 定格 / ピーク リフロー
- MTBF/FIT 推定値
- 使用原材料
- 認定試験結果
- 継続的な信頼性モニタ試験結果
- ファブの拠点
- 組み立てを実施した拠点