패키징 정보
패키지 | 핀 VQFN (RGZ) | 48 |
작동 온도 범위(°C) -40 to 85 |
패키지 수량 | 캐리어 2,500 | LARGE T&R |
ADC3224의 주요 특징
- Dual channel
- 12-Bit resolution
- Single supply: 1.8 V
- Serial LVDS interface (SLVDS)
- Flexible input clock buffer with divide-by-1, -2, -4
- SNR = 70.2 dBFS, SFDR = 87 dBc at fIN = 70 MHz
- Ultra-low power consumption:
- 116 mW/Ch at 125 MSPS
- Channel isolation: 105 dB
- Internal dither and chopper
- Support for multi-chip synchronization
- Pin-to-pin compatible with 14-Bit version
- Package: VQFN-48 (7 mm × 7 mm)
ADC3224에 대한 설명
The ADC322x are a high-linearity, ultra-low power, dual-channel, 12-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC322x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. Optionally, a one-wire serial LVDS interface is available. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.