홈 마이크로컨트롤러(MCU) 및 프로세서 Arm 기반 프로세서
홈
마이크로컨트롤러(MCU) 및 프로세서
Arm 기반 프로세서

AM1802

활성

Sitara 프로세서: Arm9, LPDDR, DDR2, 이더넷

지금 주문
데이터 시트
정오표

AM1802

활성
데이터 시트 지금 주문

제품 상세 정보

Arm CPU 1 Arm9 Arm (max) (MHz) 300 Coprocessors PRU-ICSS CPU 32-bit Protocols Ethernet Ethernet MAC 1-Port 10/100 Operating system Linux, RTOS Security Device identity, Memory protection Rating Catalog Operating temperature range (°C) -40 to 90
Arm CPU 1 Arm9 Arm (max) (MHz) 300 Coprocessors PRU-ICSS CPU 32-bit Protocols Ethernet Ethernet MAC 1-Port 10/100 Operating system Linux, RTOS Security Device identity, Memory protection Rating Catalog Operating temperature range (°C) -40 to 90
NFBGA (ZCE) 361 169 mm² 13 x 13 NFBGA (ZWT) 361 256 mm² 16 x 16
  • 300-MHzARM926EJ-S RISC MPU
  • ARM926EJ-S Core
    • 32-Bit and 16-Bit (Thumb) Instructions
    • Single-Cycle MAC
    • ARM Jazelle Technology
    • Embedded ICE-RT for Real-Time Debug
  • ARM9 Memory Architecture
    • 16KB of Instruction Cache
    • 16KB of Data Cache
    • 8KB of RAM (Vector Table)
    • 64KB of ROM
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Channel Controllers
    • 3 Transfer Controllers
    • 64 Independent DMA Channels
    • 16 Quick DMA Channels
    • Programmable Transfer Burst Size
  • 128KB of On-Chip Memory
  • 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM with 128-MB Address Space
    • DDR2/Mobile DDR Memory Controller with one of the following:
      • 16-Bit DDR2 SDRAM with 256-MB Address Space
      • 16-Bit mDDR SDRAM with 256-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • With Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • Two Serial Peripheral Interfaces (SPIs) Each with Multiple Chip Selects
  • One Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces with Secure Data I/O (SDIO) Interfaces
  • One Master and Slave Inter-Integrated Circuit (I2C Bus)
  • USB 2.0 OTG Port with Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1, 2, 3, 4 (Control, Bulk, Interrupt or ISOC) RX and TX
  • One Multichannel Audio Serial Port (McASP):
    • Transmit and Receive Clocks
    • Two Clock Zones and 16 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant
    • MII Media-Independent Interface
    • RMII Reduced Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail
  • Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Packages:
    • 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
    • 361-Ball PBGA [ZWT Suffix], 0.80-mm Ball Pitch
  • Industrial Temperature
  • 300-MHzARM926EJ-S RISC MPU
  • ARM926EJ-S Core
    • 32-Bit and 16-Bit (Thumb) Instructions
    • Single-Cycle MAC
    • ARM Jazelle Technology
    • Embedded ICE-RT for Real-Time Debug
  • ARM9 Memory Architecture
    • 16KB of Instruction Cache
    • 16KB of Data Cache
    • 8KB of RAM (Vector Table)
    • 64KB of ROM
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Channel Controllers
    • 3 Transfer Controllers
    • 64 Independent DMA Channels
    • 16 Quick DMA Channels
    • Programmable Transfer Burst Size
  • 128KB of On-Chip Memory
  • 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM with 128-MB Address Space
    • DDR2/Mobile DDR Memory Controller with one of the following:
      • 16-Bit DDR2 SDRAM with 256-MB Address Space
      • 16-Bit mDDR SDRAM with 256-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • With Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • Two Serial Peripheral Interfaces (SPIs) Each with Multiple Chip Selects
  • One Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces with Secure Data I/O (SDIO) Interfaces
  • One Master and Slave Inter-Integrated Circuit (I2C Bus)
  • USB 2.0 OTG Port with Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1, 2, 3, 4 (Control, Bulk, Interrupt or ISOC) RX and TX
  • One Multichannel Audio Serial Port (McASP):
    • Transmit and Receive Clocks
    • Two Clock Zones and 16 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant
    • MII Media-Independent Interface
    • RMII Reduced Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail
  • Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Packages:
    • 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
    • 361-Ball PBGA [ZWT Suffix], 0.80-mm Ball Pitch
  • Industrial Temperature

The AM1802 ARM microprocessor is a low-power applications processor based on ARM926EJ-S.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM core processor has separate 16-KB instruction and 16-KB data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The peripheral set includes: a 10/100 Mbps Ethernet media access controller (EMAC) with a management data input/output (MDIO) module; one USB2.0 OTG interface; one inter-integrated circuit (I2C Bus) interface; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two serial peripheral interfaces (SPIs) with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller.

The EMAC provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM processor. These tools include C compilers, and scheduling, and a Windows debugger interface for visibility into source code execution.

The AM1802 ARM microprocessor is a low-power applications processor based on ARM926EJ-S.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM core processor has separate 16-KB instruction and 16-KB data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The peripheral set includes: a 10/100 Mbps Ethernet media access controller (EMAC) with a management data input/output (MDIO) module; one USB2.0 OTG interface; one inter-integrated circuit (I2C Bus) interface; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two serial peripheral interfaces (SPIs) with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller.

The EMAC provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM processor. These tools include C compilers, and scheduling, and a Windows debugger interface for visibility into source code execution.
filter 기타 Arm 기반 프로세서 찾기
다운로드 스크립트와 함께 비디오 보기 동영상

관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 유사한 기능
AM3352 활성 Sitara™ 프로세서: Arm Cortex-A8, 1Gb 이더넷, 디스플레이, CAN This device covers more functions with newer technology including an Arm Cortex-A8 core and Gb Ethernet

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
27개 모두 보기
유형 직함 날짜
* Data sheet AM1802 ARM Microprocessor datasheet (Rev. E) PDF | HTML 2014/03/21
* Errata AM1802 ARM Microprocessor Silicon Errata (Revs 2.3, 2.1 and 2.0) (Rev. H) 2014/09/17
User guide ARM Assembly Language Tools v20.2.0.LTS User's Guide (Rev. Z) PDF | HTML 2023/03/30
User guide ARM Optimizing C/C++ Compiler v20.2.0.LTS User's Guide (Rev. W) PDF | HTML 2023/03/30
Application note Programming mDDR/DDR2 EMIF on OMAP-L1x/C674x 2019/12/20
User guide ARM Assembly Language Tools v19.6.0.STS User's Guide (Rev. X) 2019/06/03
User guide ARM Optimizing C/C++ Compiler v19.6.0.STS User's Guide (Rev. U) 2019/06/03
Application note Programming PLL Controllers on OMAP-L1x8/C674x/AM18xx 2019/04/25
Application note General Hardware Design/BGA PCB Design/BGA 2019/02/22
Application note Using the AM18xx Bootloader (Rev. D) PDF | HTML 2019/01/22
User guide ARM Assembly Language Tools v18.12.0.LTS User's Guide (Rev. W) 2018/11/19
User guide ARM Optimizing C/C++ Compiler v18.12.0.LTS User's Guide (Rev. T) 2018/11/19
User guide How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 2018/09/24
User guide ARM Assembly Language Tools v18.1.0.LTS User's Guide (Rev. U) 2018/01/16
User guide ARM Optimizing C/C++ Compiler v18.1.0.LTS User's Guide (Rev. R) 2018/01/16
User guide ARM Assembly Language Tools v17.9.0.STS User's Guide (Rev. T) 2017/09/30
User guide ARM Optimizing C/C++ Compiler v17.9.0.STS User's Guide (Rev. Q) 2017/09/30
User guide ARM Assembly Language Tools v17.6.0.STS User's Guide (Rev. S) 2017/06/21
User guide ARM Optimizing C/C++ Compiler v17.6.0.STS User's Guide (Rev. P) 2017/06/21
User guide AM1802 ARM Microprocessor Technical Reference Manual (Rev. C) 2016/09/12
User guide ARM Assembly Language Tools v16.9.0.LTS User's Guide (Rev. P) 2016/04/30
User guide ARM Optimizing C/C++ Compiler v16.9.0.LTS User's Guide (Rev. M) 2016/04/30
Technical article Spring has sprung. A sale has sprung. PDF | HTML 2016/04/04
User guide ARM Assembly Language Tools v5.2 User's Guide (Rev. M) 2014/11/05
User guide ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J) 2014/11/05
Application note AM18xx Pin Multiplexing Utility (Rev. A) 2011/12/06
Application note AM18x power consumption summary 2010/08/30

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

디버그 프로브

TMDSEMU200-U — XDS200 USB 디버그 프로브

XDS200은 TI 임베디드 디바이스 디버깅에 사용되는 디버그 프로브(에뮬레이터)입니다. XDS200은 저렴한 XDS110 및 고성능 XDS560v2에 비해 저렴한 비용으로 우수한 성능을 균형 있게 제공합니다. 단일 포드에서 광범위한 표준(IEEE1149.1, IEEE1149.7, SWD)을 지원합니다. 모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 Arm® 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 코어 추적의 경우 XDS560v2 PRO TRACE가 (...)

TI.com에서 구매 불가
디버그 프로브

TMDSEMU560V2STM-U — XDS560v2 시스템 추적 USB 디버그 프로브

XDS560v2는 디버그 프로브의 XDS560™ 제품군 중 최고의 성능을 가진 제품으로, 기존의 JTAG 표준(IEEE1149.1)과 cJTAG(IEEE1149.7)를 모두 지원합니다. SWD(직렬 와이어 디버그)는 지원하지 않습니다.

모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 ARM 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 추적의 경우 XDS560v2 PRO TRACE가 필요합니다.

XDS560v2는 MIPI HSPT 60핀 커넥터(TI 14핀, (...)

TI.com에서 구매 불가
디버그 프로브

TMDSEMU560V2STM-UE — XDS560v2 시스템 추적 USB 및 이더넷 디버그 프로브

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

TI.com에서 구매 불가
소프트웨어 개발 키트(SDK)

LINUXEZSDK-SITARA — Sitara™ 프로세서용 EZSDK(Linux EZ 소프트웨어 개발 키트)

SITARA LINUX SDK

Linux Software Development Kits (SDK) provide Sitara™ developers with an easy set up and quick out-of-box experience that is specific to and highlights the features of TI's ARM processors. Launching demos, benchmarks and applications is a snap with the included graphical user (...)

View Options
소프트웨어 개발 키트(SDK)

PRU-SWPKG — Programmable Real-time Unit (PRU) Software Support Package

The PRU Software Support Package is an add-on package that provides a framework and examples for developing software for the Programmable Real-time Unit sub-system and Industrial Communication Sub-System (PRU-ICSS) in the supported TI processors.  The PRU-ICSS achieves deterministic, real-time (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
Arm 기반 프로세서
AM1802 — Sitara 프로세서: Arm9, LPDDR, DDR2, 이더넷 AM1806 — Sitara 프로세서: Arm9, LPDDR, DDR2, 디스플레이 AM1808 — Sitara 프로세서: Arm9, LPDDR, DDR2, 디스플레이, 이더넷 AM1810 — Sitara 프로세서: Arm9, LPDDR, DDR2, 디스플레이, 이더넷, PROFIBUS AM4377 — Sitara 프로세서: Arm Cortex-A9, PRU-ICSS, EtherCAT AM4378 — Sitara 프로세서: Arm Cortex-A9, PRU-ICSS, 3D 그래픽
소프트웨어
소프트웨어 개발 키트(SDK)
PRU-SWPKG — PRU(Programmable Real-time Unit) 소프트웨어 지원 패키지
다운로드 옵션
소프트웨어 개발 키트(SDK)

WINCESDK-AM1XOMAPL1X — Windows® 임베디드 컴팩트/CE SDK - ARM9™기반 AM18x, OMAP-L13x 프로세서

Microsoft Windows Embedded Compact (WEC7) andCE (WinCE 6.0) operating systems are optimized for embedded devices that require minimum storage based on a componentized architecture.

WinCE BSPs for ARM9-based processors are now available fromAdeneo Embedded.

파트너 사이트 방문
드라이버 또는 라이브러리

STARTERWARE-SITARA — ARM® 기반 TI Sitara 프로세서용 StarterWare

StarterWare provides C-based no-OS platform support for TI's ARM9™ and ARM® Cortex™ A8 based devices. StarterWare provides device abstraction layer libraries, peripheral programming examples such as Ethernet, graphics and USB, and board level example applications. StarterWare can be (...)
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IDE, 구성, 컴파일러 또는 디버거

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

이 설계 리소스는 이러한 범주의 제품 대부분을 지원합니다.

제품 세부 정보 페이지에서 지원을 확인하십시오.
시작 다운로드 옵션
운영 체제(OS)

MG-3P-NUCLEUS-RTOS — Mentor Graphics Nucleus RTOS

Software driven power management is crucial for battery operated or low power budget embedded systems. Embedded developers can now take advantage of the latest power saving features in popular TI devices with the built-in Power Management Framework in the Nucleus RTOS. Developers specify (...)
발송: Mentor Graphics Corporation
파트너 사이트 방문
시뮬레이션 모델

AM1802 ZCE IBIS Model

SPRM604.ZIP (120 KB) - IBIS Model
다운로드
시뮬레이션 모델

AM1802 ZWT BSDL Model

SPRM517.ZIP (8 KB) - BSDL Model
다운로드
시뮬레이션 모델

AM1802 ZWT IBIS Model (Rev. A)

SPRM518A.ZIP (121 KB) - IBIS Model
다운로드
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
NFBGA (ZCE) 361 Ultra Librarian
NFBGA (ZWT) 361 Ultra Librarian
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

포럼 주제 모두 보기(영문)

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품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

동영상