CD4068B-MIL

활성

CMOS 8입력 NAND/AND 게이트

제품 상세 정보

Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Number of channels 1 Inputs per channel 8 IOL (max) (mA) 1.5 IOH (max) (mA) -1.5 Input type Standard CMOS Output type Push-Pull Features Standard speed (tpd > 50ns) Data rate (max) (Mbps) 8 Rating Military Operating temperature range (°C) -55 to 125
Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Number of channels 1 Inputs per channel 8 IOL (max) (mA) 1.5 IOH (max) (mA) -1.5 Input type Standard CMOS Output type Push-Pull Features Standard speed (tpd > 50ns) Data rate (max) (Mbps) 8 Rating Military Operating temperature range (°C) -55 to 125
CDIP (J) 14 130.4652 mm² 19.56 x 6.67
  • Medium Speed Operation:
       tPHL, tPLH=75 ns (typ.) at VDD = 10 V
  • Buffered inputs and outputs
  • 5-V, 10-V, and 15-V parametric ratings
  • Standardized symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (over full package-temperature range) =
         1 V at VDD = 5 V
         2 V at VDD = 10 V
      2.5 V at VDD = 15 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor

  • Medium Speed Operation:
       tPHL, tPLH=75 ns (typ.) at VDD = 10 V
  • Buffered inputs and outputs
  • 5-V, 10-V, and 15-V parametric ratings
  • Standardized symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (over full package-temperature range) =
         1 V at VDD = 5 V
         2 V at VDD = 10 V
      2.5 V at VDD = 15 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor

CD4068B NAND/AND gate provides the system designer with direct implementation of the positive-logic 8-input NAND and AND functions and supplements the existing family of CMOS gates.

The CD4068B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4068B NAND/AND gate provides the system designer with direct implementation of the positive-logic 8-input NAND and AND functions and supplements the existing family of CMOS gates.

The CD4068B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

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기술 자료

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7개 모두 보기
유형 직함 날짜
* Data sheet CD4068B TYPES datasheet (Rev. C) 2003/08/21
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics 2001/12/03

설계 및 개발

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패키지 CAD 기호, 풋프린트 및 3D 모델
CDIP (J) 14 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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