CD4071B

활성

4채널 2입력 3V~18V OR 게이트

지금 주문

데이터 시트

document-pdfAcrobat CD4071B, CD4072B, CD4075B TYPES datasheet (Rev. D) (영어)

CD4071B

활성

데이터 시트

지금 주문

제품 상세 정보

Technology family

CD4000

Supply voltage (min) (V)

Supply voltage (max) (V)

Number of channels

Inputs per channel

IOL (max) (mA)

6.8

IOH (max) (mA)

-6.8

Input type

Standard CMOS

Output type

Push-Pull

Features

Standard speed (tpd > 50ns)

Data rate (max) (Mbps)

Rating

Catalog

Operating temperature range (°C)

-55 to 125

Technology family

CD4000

Supply voltage (min) (V)

Supply voltage (max) (V)

Number of channels

Inputs per channel

IOL (max) (mA)

6.8

IOH (max) (mA)

-6.8

Input type

Standard CMOS

Output type

Push-Pull

Features

Standard speed (tpd > 50ns)

Data rate (max) (Mbps)

Rating

Catalog

Operating temperature range (°C)

-55 to 125

PDIP (N)

181.42 mm² 19.3 x 9.4

SOIC (D)

51.9 mm² 8.65 x 6

SOP (NS)

79.56 mm² 10.2 x 7.8

TSSOP (PW)

32 mm² 5 x 6.4

Medium-Speed Operation - t_PLH, t_PHL = 60 ns (typ.) at V_DD = 10 V
100% tested for quiescent current at 20 V
Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Standardized, symmetrical output characteristics
Noise margin (full package-temperature range):
     1 V at V_DD = 5 V
     2 V at V_DD = 10 V
  2.5 V at V_DD = 15 V
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor

Medium-Speed Operation - t_PLH, t_PHL = 60 ns (typ.) at V_DD = 10 V
100% tested for quiescent current at 20 V
Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Standardized, symmetrical output characteristics
Noise margin (full package-temperature range):
     1 V at V_DD = 5 V
     2 V at V_DD = 10 V
  2.5 V at V_DD = 15 V
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor

CD4071B, CD4072B and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates.

The CD4071B, CD4072B, and CD4075B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes) and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4071B, CD4072B and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates.

filter

기타 OR 게이트 찾기

다운로드 스크립트와 함께 비디오 보기 동영상

관심 가지실만한 유사 제품

open-in-new

대안 비교

비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀

CD74AC32

활성

4채널, 2입력, 1.5V~5.5V 24mA 드라이브 강도 OR 게이트 Smaller voltage range (2V to 6V), shorter average propagation delay (7ns), higher average drive strength (24mA)

기술 자료

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7개 모두 보기

	유형	직함	날짜
*	Data sheet	CD4071B, CD4072B, CD4075B TYPES datasheet (Rev. D)	2003/08/21
	Selection guide	Logic Guide (Rev. AB)	2017/06/12
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	2015/12/02
	User guide	LOGIC Pocket Data Book (Rev. B)	2007/01/16
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	2004/07/08
	User guide	Signal Switch Data Book (Rev. A)	2003/11/14
	Application note	Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics	2001/12/03