홈 로직 및 전압 변환 플립플롭, 래치 및 레지스터 시프트 레지스터
홈
로직 및 전압 변환
플립플롭, 래치 및 레지스터
시프트 레지스터

CD4517B-MIL

활성

CMOS 듀얼 64단계 정적 시프트 레지스터

지금 주문
데이터 시트

CD4517B-MIL

활성
데이터 시트 지금 주문

제품 상세 정보

Configuration Universal Bits (#) 64 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type Standard CMOS Output type Push-Pull Clock frequency (MHz) 8.5 IOL (max) (mA) 4.2 IOH (max) (mA) -4.2 Supply current (max) (µA) 3000 Features Balanced outputs, Positive input clamp diode, Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Military
Configuration Universal Bits (#) 64 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type Standard CMOS Output type Push-Pull Clock frequency (MHz) 8.5 IOL (max) (mA) 4.2 IOH (max) (mA) -4.2 Supply current (max) (µA) 3000 Features Balanced outputs, Positive input clamp diode, Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92
  • Low quiescent current - 10 nA/pkg (typ.) at VDD = 5 V
  • Clock frequency 12 MHz (typ.) at VDD = 10 V
  • Schmitt trigger clock inputs allow operation with very slow clock rise and fall times
  • Capable of driving two low-power TTL loads, one low-power Schottky TTL load, or two HTL loads
  • Three-state outputs
  • 100% tested for quiescent current at 20 V
  • Standardized, symmetrical output characteristics
  • 5-V, 10-V and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
  • Applications:
    Time-delay circuits
    Scratch-pad memories
    General-purpose serial shift-register applications
  • Low quiescent current - 10 nA/pkg (typ.) at VDD = 5 V
  • Clock frequency 12 MHz (typ.) at VDD = 10 V
  • Schmitt trigger clock inputs allow operation with very slow clock rise and fall times
  • Capable of driving two low-power TTL loads, one low-power Schottky TTL load, or two HTL loads
  • Three-state outputs
  • 100% tested for quiescent current at 20 V
  • Standardized, symmetrical output characteristics
  • 5-V, 10-V and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
  • Applications:
    Time-delay circuits
    Scratch-pad memories
    General-purpose serial shift-register applications

CD4517B dual 64-stage static shift register consists of two independent registers each having a clock, data, and write enable input and outputs accessible at taps following the 16th, 32nd, 48th, and 64th stages. These taps also serve as input points allowing data to be inputted at the 17th, 33rd, and 49th stages when the write enable input is a logic 1 and the clock goes through a low-to-high transition. The truth table indicates how the clock and write enable inputs control the operation of the CD4517B. Inputs at the intermediate taps allow entry of 64 bits into the register with 16 clock pulses. The 3-state outputs permit connection of this device to an external bus.

The CD4517B is supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes), 16-lead dual-in-line plastic packages (E suffix), and in chip form (H suffix).

CD4517B dual 64-stage static shift register consists of two independent registers each having a clock, data, and write enable input and outputs accessible at taps following the 16th, 32nd, 48th, and 64th stages. These taps also serve as input points allowing data to be inputted at the 17th, 33rd, and 49th stages when the write enable input is a logic 1 and the clock goes through a low-to-high transition. The truth table indicates how the clock and write enable inputs control the operation of the CD4517B. Inputs at the intermediate taps allow entry of 64 bits into the register with 16 clock pulses. The 3-state outputs permit connection of this device to an external bus.

The CD4517B is supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes), 16-lead dual-in-line plastic packages (E suffix), and in chip form (H suffix).
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다운로드

기술 자료

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1개 모두 보기
유형 직함 날짜
* Data sheet CMOS Dual 64-Stage Static Shift Register datasheet 1998/11/21

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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포럼 주제 모두 보기(영문)

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