CD74AC374

Name: CD74AC374
Brand: TI
SKU: CD74AC374
Price: 0.61 USD

활성

3상 출력을 지원하는 8진 D형 플립플롭

지금 주문

데이터 시트

document-pdfAcrobat CDx4AC374, CDx4ACT374, CD74AC534 Octal D-Type Flip-Flops, 3-State Positive-Edge Triggered datasheet (Rev. A) (영어) PDF | HTML

CD74AC374

활성

데이터 시트

지금 주문

제품 상세 정보

Number of channels

Technology family

Supply voltage (min) (V)

1.5

Supply voltage (max) (V)

5.5

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

110

IOL (max) (mA)

IOH (max) (mA)

-24

Supply current (max) (µA)

160

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-55 to 125

Rating

Catalog

Number of channels

Technology family

Supply voltage (min) (V)

1.5

Supply voltage (max) (V)

5.5

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

110

IOL (max) (mA)

IOH (max) (mA)

-24

Supply current (max) (µA)

160

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-55 to 125

Rating

Catalog

PDIP (N)

228.702 mm² 24.33 x 9.4

SOIC (DW)

131.84 mm² 12.8 x 10.3

SCR-Latch-up-resistant CMOS process and circuit design
Speed of bipolar FAST*/AS/S with significantly reduced power consumption
Balanced propagation delays
AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply
± 24mA output drive current
- Fanout to 15 FAST* ICs
- Drives 50ohm transmission lines

⁽¹⁾FAST is a Registered Trademark of Fairchild Semiconductor Corp.

SCR-Latch-up-resistant CMOS process and circuit design
Speed of bipolar FAST*/AS/S with significantly reduced power consumption
Balanced propagation delays
AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply
± 24mA output drive current
- Fanout to 15 FAST* ICs
- Drives 50ohm transmission lines

⁽¹⁾FAST is a Registered Trademark of Fairchild Semiconductor Corp.

The eight flip-flops of the ’AC374 devices are D-type edge-triggered flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

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