CD74HC299

활성

3상 출력을 지원하는 고속 CMOS 로직 8비트 범용 시프트 레지스터

제품 상세 정보

Configuration Universal Bits (#) 8 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type 3-State Clock frequency (MHz) 24 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Supply current (max) (µA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Catalog
Configuration Universal Bits (#) 8 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type 3-State Clock frequency (MHz) 24 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Supply current (max) (µA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Catalog
PDIP (N) 20 228.702 mm² 24.33 x 9.4 SOIC (DW) 20 131.84 mm² 12.8 x 10.3
  • Buffered Inputs
  • Four Operating Modes: Shift Left, Shift Right, Load and Store
  • Can be Cascaded for N-Bit Word Lengths
  • I/O0 – I/O7 Bus Drive Capability and Three-State for Bus Oriented Applications
  • Typical fMAX = 50MHz at VCC =5V, CL = 15pF, TA = 25°C
  • Fanout (Over Temperature Range)
    • Standard Outputs. . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor

  • Buffered Inputs
  • Four Operating Modes: Shift Left, Shift Right, Load and Store
  • Can be Cascaded for N-Bit Word Lengths
  • I/O0 – I/O7 Bus Drive Capability and Three-State for Bus Oriented Applications
  • Typical fMAX = 50MHz at VCC =5V, CL = 15pF, TA = 25°C
  • Fanout (Over Temperature Range)
    • Standard Outputs. . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor

The ’HC259 and ’HCT299 are 8-bit shift/storage registers with three-state bus interface capability. The register has four synchronous-operating modes controlled by the two select inputs as shown in the mode select (S0, S1) table. The mode select, the serial data (DS0, DS7) and the parallel data (I/O0 – I/O7) respond only to the low-to-high transition of the clock (CP) pulse. S0, S1 and data inputs must be one set-up time prior to the clock positive transition.

The Master Reset (MR)\ is an asynchronous active low input. When MR\ output is low, the register is cleared regardless of the status of all other inputs. The register can be expanded by cascading same units by tying the serial output (Q0) to the serial data (DS7) input of the preceding register, and tying the serial output (Q7) to the serial data (DS0) input of the following register. Recirculating the (n x 8) bits is accomplished by tying the Q7 of the last stage to the DS0 of the first stage.

The three-state input/output I(/O) port has three modes of operation:

1. Both output enable (OE1\ and OE2\) inputs are low and S0 or S1 or both are low, the data in the register is presented at the eight outputs.

2. When both S0 and S1 are high, I/O terminals are in the high impedance state but being input ports, ready for par-allel data to be loaded into eight registers with one clock transition regardless of the status of OE1\ and OE2\.

3. Either one of the two output enable inputs being high will force I/O terminals to be in the off-state. It is noted that each I/O terminal is a three-state output and a CMOS buffer input.

The ’HC259 and ’HCT299 are 8-bit shift/storage registers with three-state bus interface capability. The register has four synchronous-operating modes controlled by the two select inputs as shown in the mode select (S0, S1) table. The mode select, the serial data (DS0, DS7) and the parallel data (I/O0 – I/O7) respond only to the low-to-high transition of the clock (CP) pulse. S0, S1 and data inputs must be one set-up time prior to the clock positive transition.

The Master Reset (MR)\ is an asynchronous active low input. When MR\ output is low, the register is cleared regardless of the status of all other inputs. The register can be expanded by cascading same units by tying the serial output (Q0) to the serial data (DS7) input of the preceding register, and tying the serial output (Q7) to the serial data (DS0) input of the following register. Recirculating the (n x 8) bits is accomplished by tying the Q7 of the last stage to the DS0 of the first stage.

The three-state input/output I(/O) port has three modes of operation:

1. Both output enable (OE1\ and OE2\) inputs are low and S0 or S1 or both are low, the data in the register is presented at the eight outputs.

2. When both S0 and S1 are high, I/O terminals are in the high impedance state but being input ports, ready for par-allel data to be loaded into eight registers with one clock transition regardless of the status of OE1\ and OE2\.

3. Either one of the two output enable inputs being high will force I/O terminals to be in the off-state. It is noted that each I/O terminal is a three-state output and a CMOS buffer input.

다운로드 스크립트와 함께 비디오 보기 동영상

관심 가지실만한 유사 제품

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비교 대상 장치와 유사한 기능
SN74HC595 활성 3상 출력 레지스터를 지원하는 8비트 시프트 레지스터 Voltage range (2V to 6V), average drive strength (8mA), average propagation delay (20ns)

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
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15개 모두 보기
유형 직함 날짜
* Data sheet CD54HC299, CD74HC299, CD54HCT299, CD74HCT299 datasheet (Rev. C) 2003/04/16
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022/12/15
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note Designing With Logic (Rev. C) 1997/06/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 1996/05/01
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996/04/01

설계 및 개발

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평가 보드

14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈

14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.

사용 설명서: PDF | HTML
TI.com에서 구매 불가
패키지 CAD 기호, 풋프린트 및 3D 모델
PDIP (N) 20 Ultra Librarian
SOIC (DW) 20 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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