CY54FCT377T
- Function, Pinout, and Drive Compatible With FCT and F Logic
- Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
- Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
- Ioff Supports Partial-Power-Down Mode Operation
- Matched Rise and Fall Times
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
- Fully Compatible With TTL Input and Output Logic Levels
- Clock Enable for Address and Data Synchronization Application
- Eight Edge-Triggered D-Type Flip-Flops
- CY54FCT377T
- 32-mA Output Sink Current
- 12-mA Output Source Current
- CY74FCT377T
- 64-mA Output Sink Current
- 32-mA Output Source Current
The \x92FCT377T devices have eight triggered D-type flip-flops with individual data (D) inputs. The common buffered clock (CP) inputs load all flip-flops simultaneously when the clock-enable (CE\) input is low. The register is fully edge triggered. The state of each D input at one setup time before the low-to-high clock transition is transferred to the corresponding flip-flop output (O). CE\ must be stable only one setup time prior to the low-to-high clock transition for predictable operation.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
기술 자료
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1개 모두 보기 | 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | 8-Bit Registers datasheet (Rev. A) | 2001/10/01 |
주문 및 품질
포함된 정보:
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
포함된 정보:
- 팹 위치
- 조립 위치