DRV8351-SEP
- 40V Three Phase Half-Bridge Gate driver
- Drives N-Channel MOSFETs (NMOS)
- Gate Driver Supply (GVDD): 5-15V
- MOSFET supply (SHx) supports up to 40V
- Target Radiation Performance
- SEL, SEB, and SET immune up to LET = 43 MeV-cm2 /mg
- SET and SEFI characterized up to LET = 43 MeV-cm2 /mg
- TID assured for every wafer lot up to 30 krad(Si)
- TID characterized up to 30 krad(Si)
- Space-enhanced plastic (space EP):
- Controlled Baseline
- One Assembly/Test Site
- One Fabrication site
- Extended Product Life Cycle
- Product Traceability
- Integrated Bootstrap Diodes
- Supports Inverting and Non-Inverting INLx inputs
- Bootstrap gate drive architecture
- 750mA source current
- 1.5- sink current
- Low leakage current on SHx pins (<55µA)
- Absolute maximum BSTx voltage up to 57.5V
- Supports negative transients up to -22V on SHx
- Built-in cross conduction prevention
- Fixed deadtime insertion of 200nS
- Supports 3.3V and 5V logic inputs with 20V Abs max
- 4nS typical propagation delay matching
- Compact TSSOP package
- Efficient system design with Power Blocks
- Integrated protection features
- BST undervoltage lockout (BSTUV)
- GVDD undervoltage (GVDDUV)
DRV8351-SEP is a three phase half-bridge gate driver, capable of driving high-side and low-side N-channel power MOSFETs. The DRV8351-SEPD generates the correct gate drive voltages using an integrated bootstrap diode and external capacitor for the high-side MOSFETs. GVDD is used to generate gate drive voltage for the low-side MOSFETs. The Gate Drive architecture supports peak up to 750mA source and 1.5A sink currents.
The phase pins SHx are able to tolerate significant negative voltage transients; while high side gate driver supply BSTx and GHx can support higher positive voltage transients (57.5V) abs max voltage which improve the robustness of the system. Small propagation delay and delay matching specifications minimize the dead-time requirement which further improves efficiency. Undervoltage protection is provided for both low and high sides through GVDD and BST undervoltage lockout.
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | DRV8351-SEP: 40-V Three-Phase BLDC Gate Driver datasheet | PDF | HTML | 2024/12/09 |
| * | Radiation & reliability report | DRV8351-SEP Total Ionizing Dose (TID) Report | PDF | HTML | 2024/12/12 |
설계 및 개발
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DRV8351EVM — DRV8351 평가 모듈
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| TSSOP (PW) | 20 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치