SN54AS174

Name: SN54AS174
Brand: TI
SKU: SN54AS174
Price: 46.142 USD

활성

클리어를 지원하는 16진/쿼드러플 D형 플립플롭

지금 주문

데이터 시트

document-pdfAcrobat Hex/Quadruple D-Type Flip-Flops With Clear datasheet (Rev. E) (영어)

SN54AS174

활성

데이터 시트

지금 주문

제품 상세 정보

Number of channels

6

Technology family

AS

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

Bipolar

Output type

Push-Pull

Clock frequency (max) (MHz)

100

IOL (max) (mA)

20

IOH (max) (mA)

-2

Supply current (max) (µA)

45000

Features

Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-55 to 125

Rating

Military

Number of channels

6

Technology family

AS

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

Bipolar

Output type

Push-Pull

Clock frequency (max) (MHz)

100

IOL (max) (mA)

20

IOH (max) (mA)

-2

Supply current (max) (µA)

45000

Features

Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-55 to 125

Rating

Military

CDIP (J)

16

135.3552 mm² 19.56 x 6.92

’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs
’ALS175 and ’AS175B Contain Four Flip-Flops With Double-Rail Outputs
Buffered Clock and Direct-Clear Inputs
Applications Include:
- Buffer/Storage Registers
- Shift Registers
- Pattern Generators
Fully Buffered Outputs for Maximum Isolation From External Disturbances (’AS Only)

’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs
’ALS175 and ’AS175B Contain Four Flip-Flops With Double-Rail Outputs
Buffered Clock and Direct-Clear Inputs
Applications Include:
- Buffer/Storage Registers
- Shift Registers
- Pattern Generators
Fully Buffered Outputs for Maximum Isolation From External Disturbances (’AS Only)

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.

Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

These circuits are fully compatible for use with most TTL circuits.

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.

Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

These circuits are fully compatible for use with most TTL circuits.

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