SN54F74

활성

클리어 및 프리셋을 지원하는 듀얼 양극 에지 트리거 D형 플립플롭

제품 상세 정보

Number of channels 2 Technology family F Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type Push-Pull Clock frequency (max) (MHz) 80 IOL (max) (mA) 20 IOH (max) (mA) -1 Supply current (max) (µA) 16000 Features Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 2 Technology family F Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type Push-Pull Clock frequency (max) (MHz) 80 IOL (max) (mA) 20 IOH (max) (mA) -1 Supply current (max) (µA) 16000 Features Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 14 130.4652 mm² 19.56 x 6.67 CFP (W) 14 58.023 mm² 9.21 x 6.3 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
  • Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs

These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.

The SN54F74 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F74 is characterized for operation from 0°C to 70°C.

 

 

The output levels are not guaranteed to meet the minimum levels for VOH. Furthermore, this configuration is nonstable; that is, it will not persist when or returns to its inactive (high) level.

These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.

The SN54F74 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F74 is characterized for operation from 0°C to 70°C.

 

 

The output levels are not guaranteed to meet the minimum levels for VOH. Furthermore, this configuration is nonstable; that is, it will not persist when or returns to its inactive (high) level.

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관심 가지실만한 유사 제품

open-in-new 대안 비교
다른 핀 출력을 지원하지만 비교 대상 장치와 동일한 기능
신규 SN74LV2T74-EP 활성 클리어, 프리셋 및 통합 레벨 시프터를 지원하는 향상된 제품 듀얼 D형 플립플롭 Voltage range (1.65V to 5.5V), voltage translation capable

기술 자료

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11개 모두 보기
유형 직함 날짜
* Data sheet Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset datasheet (Rev. A) 1993/10/01
* SMD SN54F74 SMD 5962-97592 2016/06/21
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022/12/15
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note Designing With Logic (Rev. C) 1997/06/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01

설계 및 개발

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패키지 CAD 기호, 풋프린트 및 3D 모델
CDIP (J) 14 Ultra Librarian
CFP (W) 14 Ultra Librarian
LCCC (FK) 20 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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