SN54HC373-DIE

활성

3상 출력을 지원하는 8진 투명 D형 래치

제품 상세 정보

Number of channels 8 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Operating temperature range (°C) 25 to 25 Rating Space
Number of channels 8 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Operating temperature range (°C) 25 to 25 Rating Space
DIESALE (TD) See data sheet
  • Wide Operating Voltage Range
  • High-Current 3-State True Outputs Can
    Drive Up To 15 LSTTL Loads
  • Low Power Consumption
  • Typical tpd = 13 ns
  • Low Input Current
  • Full Parallel Access for Loading

  • Wide Operating Voltage Range
  • High-Current 3-State True Outputs Can
    Drive Up To 15 LSTTL Loads
  • Low Power Consumption
  • Typical tpd = 13 ns
  • Low Input Current
  • Full Parallel Access for Loading

This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the SN54HC373-DIE are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs.

This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the SN54HC373-DIE are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs.

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기술 자료

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16개 모두 보기
유형 직함 날짜
* Data sheet Octal Transparent D-Type Latch With 3-State Outputs, SN54HC373-DIE datasheet 2013/05/10
Selection guide TI Space Products (Rev. J) 2024/02/12
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022/12/15
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note Designing With Logic (Rev. C) 1997/06/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 1996/05/01
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996/04/01

설계 및 개발

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패키지 CAD 기호, 풋프린트 및 3D 모델
DIESALE (TD)

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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