SN54S194

활성

4비트 양방향 범용 시프트 레지스터

제품 상세 정보

Configuration Universal Bits (#) 4 Technology family S Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type Push-Pull Clock frequency (MHz) 70 IOL (max) (mA) 20 IOH (max) (mA) -1 Supply current (max) (µA) 110000 Features Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
Configuration Universal Bits (#) 4 Technology family S Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type Push-Pull Clock frequency (MHz) 70 IOL (max) (mA) 20 IOH (max) (mA) -1 Supply current (max) (µA) 110000 Features Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92 CFP (W) 16 69.319 mm² 10.3 x 6.73
  • Parallel Inputs and Outputs
  • Four Operating Modes:
    • Synchronous Parallel Load
    • Right Shift
    • Left Shift
    • Do Nothing
  • Positive Edge-Triggered Clocking
  • Direct Overriding Clear

 

  • Parallel Inputs and Outputs
  • Four Operating Modes:
    • Synchronous Parallel Load
    • Right Shift
    • Left Shift
    • Do Nothing
  • Positive Edge-Triggered Clocking
  • Direct Overriding Clear

 

These bidirectional shift registers are designed to incorporate virtually all of the features a system designer may want in a shift register. The circuit contains 46 equivalent gates and features parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely:

  • Inhibit clock (do nothing)
  • Shift right (in the direction QA toward QD)
  • Shift left (in the direction QD toward QA)
  • Parallel (broadside) load

Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into the associated flip-flops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.

Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial input.

Clocking of the shift register is inhibited when both mode control inputs are low. The mode controls of the SN54194/SN74194 should be changed only while the clock input is high.

 

These bidirectional shift registers are designed to incorporate virtually all of the features a system designer may want in a shift register. The circuit contains 46 equivalent gates and features parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely:

  • Inhibit clock (do nothing)
  • Shift right (in the direction QA toward QD)
  • Shift left (in the direction QD toward QA)
  • Parallel (broadside) load

Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into the associated flip-flops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.

Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial input.

Clocking of the shift register is inhibited when both mode control inputs are low. The mode controls of the SN54194/SN74194 should be changed only while the clock input is high.

 

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기술 자료

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10개 모두 보기
유형 직함 날짜
* Data sheet 4-Bit Bidirectional Universal Shift Registers datasheet 1988/03/01
* SMD SN54S194 SMD 7604001EA 2016/06/21
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022/12/15
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Designing With Logic (Rev. C) 1997/06/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01

설계 및 개발

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패키지 CAD 기호, 풋프린트 및 3D 모델
CDIP (J) 16 Ultra Librarian
CFP (W) 16 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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