홈 로직 및 전압 변환 플립플롭, 래치 및 레지스터 D형 플립플롭
홈
로직 및 전압 변환
플립플롭, 래치 및 레지스터
D형 플립플롭

SN54SC2T74-SEP

활성

클리어, 프리셋 및 통합 레벨 시프터를 지원하는 방사능 내성 듀얼 D형 플립플롭

지금 주문
데이터 시트

SN54SC2T74-SEP

활성
데이터 시트 지금 주문

제품 상세 정보

Number of channels 2 Technology family SCxT Supply voltage (min) (V) 1.2 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Voltage translation Operating temperature range (°C) -55 to 125 Rating Space
Number of channels 2 Technology family SCxT Supply voltage (min) (V) 1.2 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Voltage translation Operating temperature range (°C) -55 to 125 Rating Space
TSSOP (PW) 14 32 mm² 5 x 6.4
  • Vendor item drawing available, VID V62/23632-01XE
  • Total ionizing dose characterized at 30 krad (Si)
    • Total ionizing dose radiation lot acceptance testing (TID RLAT) for every wafer lot to 30 krad (Si)
  • Single-event effects (SEE) characterized:
    • Single event latch-up (SEL) immune to linear energy transfer (LET) = 43 MeV-cm2 /mg
    • Single event transient (SET) characterized to 43 MeV-cm2 /mg
  • Wide operating range of 1.2 V to 5.5 V
  • Single-supply translating gates at 5/3.3/2.5/1.8/1.2 V V CC
    • TTL compatible inputs:
      • Up translation:
        • 1.8-V – Inputs from 1.2 V
        • 2.5-V – Inputs from 1.8 V
        • 3.3-V – Inputs from 1.8 V, 2.5 V
        • 5.0-V – Inputs from 2.5 V, 3.3 V
      • Down translation:

        • 1.2-V – Inputs from 1.8 V, 2.5 V, 3.3 V, 5.0 V

        • 1.8-V – Inputs from 2.5 V, 3.3 V, 5.0 V
        • 2.5-V – Inputs from 3.3 V, 5.0 V
        • 3.3-V – Inputs from 5.0 V
  • 5.5 V tolerant input pins
  • Output drive up to 25 mA AT 5-V
  • Latch-up performance exceeds 250 mA per JESD 17
  • Space enhanced plastic (SEP)
    • Controlled baseline
    • Gold bondwire
    • NiPdAu lead finish
    • One assembly and test site
    • One fabrication site
    • Military (–55°C to 125°C) temperature range
    • Extended product life cycle
    • Product traceability
    • Meets NASAs ASTM E595 outgassing specification
  • Vendor item drawing available, VID V62/23632-01XE
  • Total ionizing dose characterized at 30 krad (Si)
    • Total ionizing dose radiation lot acceptance testing (TID RLAT) for every wafer lot to 30 krad (Si)
  • Single-event effects (SEE) characterized:
    • Single event latch-up (SEL) immune to linear energy transfer (LET) = 43 MeV-cm2 /mg
    • Single event transient (SET) characterized to 43 MeV-cm2 /mg
  • Wide operating range of 1.2 V to 5.5 V
  • Single-supply translating gates at 5/3.3/2.5/1.8/1.2 V V CC
    • TTL compatible inputs:
      • Up translation:
        • 1.8-V – Inputs from 1.2 V
        • 2.5-V – Inputs from 1.8 V
        • 3.3-V – Inputs from 1.8 V, 2.5 V
        • 5.0-V – Inputs from 2.5 V, 3.3 V
      • Down translation:

        • 1.2-V – Inputs from 1.8 V, 2.5 V, 3.3 V, 5.0 V

        • 1.8-V – Inputs from 2.5 V, 3.3 V, 5.0 V
        • 2.5-V – Inputs from 3.3 V, 5.0 V
        • 3.3-V – Inputs from 5.0 V
  • 5.5 V tolerant input pins
  • Output drive up to 25 mA AT 5-V
  • Latch-up performance exceeds 250 mA per JESD 17
  • Space enhanced plastic (SEP)
    • Controlled baseline
    • Gold bondwire
    • NiPdAu lead finish
    • One assembly and test site
    • One fabrication site
    • Military (–55°C to 125°C) temperature range
    • Extended product life cycle
    • Product traceability
    • Meets NASAs ASTM E595 outgassing specification

The SN54SC2T74-SEP contains two independent D-type positive-edge-triggered flip-flops. A low level at the preset ( PRE) input sets the output high. A low level at the clear ( CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q, Q) on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the input clock (CLK) signal. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q, Q). The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

The SN54SC2T74-SEP contains two independent D-type positive-edge-triggered flip-flops. A low level at the preset ( PRE) input sets the output high. A low level at the clear ( CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q, Q) on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the input clock (CLK) signal. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q, Q). The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).
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기술 자료

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5개 모두 보기
유형 직함 날짜
* Data sheet SN54SC2T74-SEPRadiation Tolerant, Dual D-Type Flip-Flop With Integrated Translation datasheet PDF | HTML 2023/11/15
* Radiation & reliability report SN54SC2T74-SEP Single Event Effects Report PDF | HTML 2024/04/04
* Radiation & reliability report SN54SC2T74-SEP Total Ionizing Dose (TID) Report PDF | HTML 2023/12/01
* Radiation & reliability report SN54SC2T74-SEP Production Flow and Reliability Report PDF | HTML 2023/11/03
Application brief TI Space Enhanced Plastic Logic Overview and Applications in Low-Earth Orbit Satellite Platforms PDF | HTML 2024/09/10

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈

14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.

사용 설명서: PDF | HTML
TI.com에서 구매 불가
평가 보드

14-24-NL-LOGIC-EVM — 14핀~24핀 비 리드 패키지용 로직 제품 일반 평가 모듈

14-24-NL-LOGIC-EVM은 14핀~24핀 BQA, BQB, RGY, RSV, RJW 또는 RHL 패키지가 있는 로직 또는 변환 디바이스를 지원하도록 설계된 유연한 평가 모듈(EVM)입니다.

사용 설명서: PDF | HTML
TI.com에서 구매 불가
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TSSOP (PW) 14 Ultra Librarian
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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