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전압 변환기 및 레벨 시프터
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SN54SC6T06-SEP

활성

방사능 내성, 6비트 인버팅 오픈 드레인 고정 방향 레벨 변환기

지금 주문
데이터 시트

SN54SC6T06-SEP

활성
데이터 시트 지금 주문

제품 상세 정보

Technology family SCxT Vout (min) (V) 1.2 Vout (max) (V) 5.5 Features Balanced outputs, Over-voltage tolerant inputs, Voltage translation Input type TTL-Compatible CMOS Output type Open-drain Rating Space Operating temperature range (°C) -55 to 125
Technology family SCxT Vout (min) (V) 1.2 Vout (max) (V) 5.5 Features Balanced outputs, Over-voltage tolerant inputs, Voltage translation Input type TTL-Compatible CMOS Output type Open-drain Rating Space Operating temperature range (°C) -55 to 125
TSSOP (PW) 14 32 mm² 5 x 6.4
  • Vendor item drawing available, VID V62/24616
  • Total ionizing dose characterized at 30 krad (Si)
    • Total ionizing dose radiation lot acceptance testing (TID RLAT) for every wafer lot to 30 krad (Si)
  • Single-event effects (SEE) characterized:
    • Single event latch-up (SEL) immune to linear energy transfer (LET) = 43 MeV-cm2 /mg
    • Single event transient (SET) characterized to 43 MeV-cm2 /mg
  • Wide operating range of 1.2V to 5.5V
  • Single-supply translating gates at 5/3.3/2.5/1.8/1.2V VCC
    • TTL compatible inputs:
      • Up translation:
        • 1.8V – Inputs from 1.2V
        • 2.5V – Inputs from 1.8V
        • 3.3V – Inputs from 1.8V, 2.5V
        • 5.0V – Inputs from 2.5V, 3.3V
      • Down translation:

        • 1.2V – Inputs from 1.8V, 2.5V, 3.3V, 5.0V

        • 1.8V – Inputs from 2.5V, 3.3V, 5.0V
        • 2.5V – Inputs from 3.3V, 5.0V
        • 3.3V – Inputs from 5.0V
  • 5.5V tolerant input pins
  • Output drive up to 25mA AT 5V
  • Latch-up performance exceeds 250mA per JESD 17
  • Space enhanced plastic (SEP)
    • Controlled baseline
    • Gold bondwire
    • NiPdAu lead finish
    • One assembly and test site
    • One fabrication site
    • Military (–55°C to 125°C) temperature range
    • Extended product life cycle
    • Product traceability
    • Meets NASAs ASTM E595 outgassing specification
  • Vendor item drawing available, VID V62/24616
  • Total ionizing dose characterized at 30 krad (Si)
    • Total ionizing dose radiation lot acceptance testing (TID RLAT) for every wafer lot to 30 krad (Si)
  • Single-event effects (SEE) characterized:
    • Single event latch-up (SEL) immune to linear energy transfer (LET) = 43 MeV-cm2 /mg
    • Single event transient (SET) characterized to 43 MeV-cm2 /mg
  • Wide operating range of 1.2V to 5.5V
  • Single-supply translating gates at 5/3.3/2.5/1.8/1.2V VCC
    • TTL compatible inputs:
      • Up translation:
        • 1.8V – Inputs from 1.2V
        • 2.5V – Inputs from 1.8V
        • 3.3V – Inputs from 1.8V, 2.5V
        • 5.0V – Inputs from 2.5V, 3.3V
      • Down translation:

        • 1.2V – Inputs from 1.8V, 2.5V, 3.3V, 5.0V

        • 1.8V – Inputs from 2.5V, 3.3V, 5.0V
        • 2.5V – Inputs from 3.3V, 5.0V
        • 3.3V – Inputs from 5.0V
  • 5.5V tolerant input pins
  • Output drive up to 25mA AT 5V
  • Latch-up performance exceeds 250mA per JESD 17
  • Space enhanced plastic (SEP)
    • Controlled baseline
    • Gold bondwire
    • NiPdAu lead finish
    • One assembly and test site
    • One fabrication site
    • Military (–55°C to 125°C) temperature range
    • Extended product life cycle
    • Product traceability
    • Meets NASAs ASTM E595 outgassing specification

The SN54SC6T06-SEP device contains six independent inverters with open-drain outputs and extended voltage operation to allow for level translation. Each inverter performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.2V, 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2V input to 1.8V output or 1.8V input to 3.3V output). Additionally, the 5V tolerant input pins enable down translation (for example 3.3V to 2.5V output).

The SN54SC6T06-SEP device contains six independent inverters with open-drain outputs and extended voltage operation to allow for level translation. Each inverter performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.2V, 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2V input to 1.8V output or 1.8V input to 3.3V output). Additionally, the 5V tolerant input pins enable down translation (for example 3.3V to 2.5V output).
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기술 자료

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8개 모두 보기
유형 직함 날짜
* Data sheet SN54SC6T06-SEP Radiation Tolerant, Hex Inverter Buffers/Drivers With Open-Drain Outputs datasheet PDF | HTML 2024/01/19
* Radiation & reliability report SN54SC6T06-SEP Production Flow and Reliability Report PDF | HTML 2024/04/10
* Radiation & reliability report SN54SC6T07-SEP Single Event Effects Radiation Report PDF | HTML 2024/02/21
* Radiation & reliability report SN54SC6T06-SEP Total Ionizing Dose (TID) Report PDF | HTML 2024/02/08
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 2024/10/02
Application brief TI Space Enhanced Plastic Logic Overview and Applications in Low-Earth Orbit Satellite Platforms PDF | HTML 2024/09/10
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024/07/12
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024/07/03

설계 및 개발

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평가 보드

14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈

14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.

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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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