SN74AC533

Name: SN74AC533
Brand: TI
SKU: SN74AC533
Price: 0.593 USD

활성

3상 출력을 지원하는 8진 트랜스페어런스 D형 래치

지금 주문

데이터 시트

document-pdfAcrobat SN54AC533, SN74AC533 datasheet (Rev. C) (영어)

SN74AC533

활성

데이터 시트

지금 주문

제품 상세 정보

Number of channels

8

Technology family

AC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

100

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

40

Features

Balanced outputs, High speed (tpd 10-50ns), Inverting output, Positive input clamp diode

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of channels

8

Technology family

AC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

100

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

40

Features

Balanced outputs, High speed (tpd 10-50ns), Inverting output, Positive input clamp diode

Operating temperature range (°C)

-40 to 85

Rating

Catalog

SOIC (DW)

20

131.84 mm² 12.8 x 10.3

2-V to 6-V V_CC Operation
Inputs Accept Voltages to 6 V
Max t_pd of 10.5 ns at 5 V
3-State Inverting Outputs Drive Bus Lines Directly
Full Parallel Access for Loading

2-V to 6-V V_CC Operation
Inputs Accept Voltages to 6 V
Max t_pd of 10.5 ns at 5 V
3-State Inverting Outputs Drive Bus Lines Directly
Full Parallel Access for Loading

The ’AC533 devices are octal transparent D-type latches with 3-state outputs. When the latch-enable (LE) input is high, the Q\ outputs follow the complements of the data (D) inputs. When LE is taken low, the Q\ outputs are latched at the inverse logic levels set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

(OE)\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, (OE)\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The ’AC533 devices are octal transparent D-type latches with 3-state outputs. When the latch-enable (LE) input is high, the Q\ outputs follow the complements of the data (D) inputs. When LE is taken low, the Q\ outputs are latched at the inverse logic levels set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

(OE)\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, (OE)\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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