홈 로직 및 전압 변환 로직 게이트 OR 게이트
홈
로직 및 전압 변환
로직 게이트
OR 게이트

SN74AHCT32-EP

활성

향상된 제품, 4채널 2입력 4.5V~5.5-V 고속(7.1ns) OR 게이트, TTL 호환 입력 지원

지금 주문
데이터 시트

SN74AHCT32-EP

활성
데이터 시트 지금 주문

제품 상세 정보

Technology family AHCT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 4 Inputs per channel 2 IOL (max) (mA) 8 IOH (max) (mA) -8 Input type TTL-Compatible CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 70 Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
Technology family AHCT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 4 Inputs per channel 2 IOL (max) (mA) 8 IOH (max) (mA) -8 Input type TTL-Compatible CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 70 Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
SOIC (D) 14 51.9 mm² 8.65 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • EPIC™ (Enhanced-Performance Implanted CMOS) Process
  • Inputs Are TTL-Voltage Compatible
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds 1000 V Per MIL-STD-833, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

EPIC is a trademark of Texas Instruments.
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • EPIC™ (Enhanced-Performance Implanted CMOS) Process
  • Inputs Are TTL-Voltage Compatible
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds 1000 V Per MIL-STD-833, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

EPIC is a trademark of Texas Instruments.

The SN74AHCT32 is a quadruple 2-input positive-OR gate. This device performs the Boolean function Y = (A\ • B\)\ or Y = A + B in positive logic.

The SN74AHCT32 is a quadruple 2-input positive-OR gate. This device performs the Boolean function Y = (A\ • B\)\ or Y = A + B in positive logic.
filter 기타 OR 게이트 찾기
다운로드 스크립트와 함께 비디오 보기 동영상

관심 가지실만한 유사 제품

open-in-new 대안 비교
다른 핀 출력을 지원하지만 비교 대상 장치와 동일한 기능
SN74LV4T32-EP 활성 향상된 제품, 로직 레벨 시프터가 있는 4채널 2입력 OR 게이트 Voltage range (1.65V to 5.5V), voltage translation capable

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
20개 모두 보기
유형 직함 날짜
* Data sheet SN74AHCT32-EP datasheet 2003/05/02
* VID SN74AHCT32-EP VID V6203658 2016/06/21
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Little Logic Guide 2018 (Rev. G) 2018/07/06
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note How to Select Little Logic (Rev. A) 2016/07/26
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004/11/04
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
Application note Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) 2002/12/02
Application note Texas Instruments Little Logic Application Report 2002/11/01
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Design guide AHC/AHCT Designer's Guide February 2000 (Rev. D) 2000/02/24
Product overview Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) 1998/04/01
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997/12/01
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note Live Insertion 1996/10/01

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

패키지 핀 CAD 기호, 풋프린트 및 3D 모델
SOIC (D) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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포럼 주제 모두 보기(영문)

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