SN74ALS164A

Name: SN74ALS164A
Brand: TI
SKU: SN74ALS164A
Price: 0.815 USD

활성

8bit 병렬 출력 직렬 시프트 레지스터

지금 주문

데이터 시트

document-pdfAcrobat 8-Bit Parallel-Out Serial Shift Register datasheet (Rev. D) (영어)

SN74ALS164A

활성

데이터 시트

지금 주문

제품 상세 정보

Configuration

Serial-in, Parallel-out

Bits (#)

8

Technology family

ALS

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

Bipolar

Output type

Push-Pull

Clock frequency (MHz)

50

IOL (max) (mA)

8

IOH (max) (mA)

-0.4

Supply current (max) (µA)

24000

Features

High speed (tpd 10-50ns)

Operating temperature range (°C)

0 to 70

Rating

Catalog

Configuration

Serial-in, Parallel-out

Bits (#)

8

Technology family

ALS

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

Bipolar

Output type

Push-Pull

Clock frequency (MHz)

50

IOL (max) (mA)

8

IOH (max) (mA)

-0.4

Supply current (max) (µA)

24000

Features

High speed (tpd 10-50ns)

Operating temperature range (°C)

0 to 70

Rating

Catalog

PDIP (N)

14

181.42 mm² 19.3 x 9.4

SOIC (D)

14

51.9 mm² 8.65 x 6

SOP (NS)

14

79.56 mm² 10.2 x 7.8

AND-Gated (Enable/Disable) Serial Inputs
Fully Buffered Clock and Serial Inputs
Direct Clear
Package Options Include Plastic Small-Outline (D) Packages and Standard Plastic (N) 300-mil DIPs

AND-Gated (Enable/Disable) Serial Inputs
Fully Buffered Clock and Serial Inputs
Direct Clear
Package Options Include Plastic Small-Outline (D) Packages and Standard Plastic (N) 300-mil DIPs

This 8-bit parallel-out serial shift register features AND-gated serial (A and B) inputs and an asynchronous clear (CLR\) input. The gated serial inputs permit control over incoming data because a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low, provided that the minimum setup-time requirements are met. Clocking occurs on the low-to-high-level transition of the clock (CLK) input. All inputs are diode clamped to minimize transmission-line effects.

The SN74ALS164A is characterized for operation from 0°C to 70°C.

This 8-bit parallel-out serial shift register features AND-gated serial (A and B) inputs and an asynchronous clear (CLR\) input. The gated serial inputs permit control over incoming data because a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low, provided that the minimum setup-time requirements are met. Clocking occurs on the low-to-high-level transition of the clock (CLK) input. All inputs are diode clamped to minimize transmission-line effects.

The SN74ALS164A is characterized for operation from 0°C to 70°C.

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