SN74AS194

활성

4비트 양방향 범용 시프트 레지스터

제품 상세 정보

Configuration Universal Bits (#) 4 Technology family AS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type Push-Pull Clock frequency (MHz) 80 IOL (max) (mA) 20 IOH (max) (mA) -2 Supply current (max) (µA) 53000 Features Very high speed (tpd 5-10ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Configuration Universal Bits (#) 4 Technology family AS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type Push-Pull Clock frequency (MHz) 80 IOL (max) (mA) 20 IOH (max) (mA) -2 Supply current (max) (µA) 53000 Features Very high speed (tpd 5-10ns) Operating temperature range (°C) 0 to 70 Rating Catalog
  • Parallel-to-Serial, Serial-to-Parallel Conversions
  • Left or Right Shifts
  • Parallel Synchronous Loading
  • Direct Overriding Clear
  • Temporary Data-Latching Capability
  • Package Options Include Plastic Small-Outline Packages (D), Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
  • Parallel-to-Serial, Serial-to-Parallel Conversions
  • Left or Right Shifts
  • Parallel Synchronous Loading
  • Direct Overriding Clear
  • Temporary Data-Latching Capability
  • Package Options Include Plastic Small-Outline Packages (D), Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

These 4-bit bidirectional universal shift registers feature parallel outputs, right-shift and left-shift serial (SR SER, SL SER) inputs, operating-mode-control (S0, S1) inputs, and a direct overriding clear (CLR\) line. The registers have four distinct modes of operation:

  • Inhibit clock (temporary data latch/do nothing)
  • Shift right (in the direction QA toward QD)
  • Shift left (in the direction QD toward QA)
  • Parallel (broadside) load

Parallel synchronous loading is accomplished by applying the four bits of data and taking both S0 and S1 high. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock (CLK) input. During loading, serial data flow is inhibited.

Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when both mode-control inputs are low.

The SN54AS194 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS194 is characterized for operation from 0°C to 70°C.

These 4-bit bidirectional universal shift registers feature parallel outputs, right-shift and left-shift serial (SR SER, SL SER) inputs, operating-mode-control (S0, S1) inputs, and a direct overriding clear (CLR\) line. The registers have four distinct modes of operation:

  • Inhibit clock (temporary data latch/do nothing)
  • Shift right (in the direction QA toward QD)
  • Shift left (in the direction QD toward QA)
  • Parallel (broadside) load

Parallel synchronous loading is accomplished by applying the four bits of data and taking both S0 and S1 high. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock (CLK) input. During loading, serial data flow is inhibited.

Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when both mode-control inputs are low.

The SN54AS194 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS194 is characterized for operation from 0°C to 70°C.

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관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 유사한 기능
SN74AHCT594 활성 출력 레지스터를 지원하는 8비트 시프트 레지스터 Voltage range (4.5V to 5.5V), average drive strength (8mA), average propagation delay (9ns)

기술 자료

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유형 직함 날짜
* Data sheet 4-Bit Bidirectional Universal Shift Registers datasheet (Rev. A) 1994/12/01

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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