SN74AUC1G32

Name: SN74AUC1G32
Brand: TI
SKU: SN74AUC1G32
Price: 0.064 USD

활성

1채널 2입력 0.8V~2.7V 초고속(2.4ns) OR 게이트

지금 주문

데이터 시트

document-pdfAcrobat SN74AUC1G32 Single 2-Input Positive-OR Gate datasheet (Rev. P) (영어) PDF | HTML

SN74AUC1G32

활성

데이터 시트

지금 주문

제품 상세 정보

Technology family

AUC

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

2.7

Number of channels

Inputs per channel

IOL (max) (mA)

IOH (max) (mA)

-9

Input type

Standard CMOS

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Data rate (max) (Mbps)

250

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

AUC

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

2.7

Number of channels

Inputs per channel

IOL (max) (mA)

IOH (max) (mA)

-9

Input type

Standard CMOS

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Data rate (max) (Mbps)

250

Rating

Catalog

Operating temperature range (°C)

-40 to 85

DSBGA (YZP)

2.1875 mm² 1.75 x 1.25

SOT-23 (DBV)

8.12 mm² 2.9 x 2.8

SOT-5X3 (DRL)

2.56 mm² 1.6 x 1.6

SOT-SC70 (DCK)

4.2 mm² 2 x 2.1

Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)
Available in the Texas Instruments NanoFree™ Package
Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
I_off Partial-Power-Down Mode and Back Drive Protection
Sub-1-V Operable
Max t_pd of 2.4 ns at 1.8 V
Low Power Consumption, 10-µA Maximum I_CC
±8-mA Output Drive at 1.8 V

Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)
Available in the Texas Instruments NanoFree™ Package
Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
I_off Partial-Power-Down Mode and Back Drive Protection
Sub-1-V Operable
Max t_pd of 2.4 ns at 1.8 V
Low Power Consumption, 10-µA Maximum I_CC
±8-mA Output Drive at 1.8 V

This single 2-input positive-OR gate is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC operation.

The SN74AUC1G32 device performs the Boolean function in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

For more information about AUC Little Logic devices, see Applications of Texas Instruments AUC Sub-1-V Little Logic Devices, SCEA027.

This single 2-input positive-OR gate is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC operation.

The SN74AUC1G32 device performs the Boolean function in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

For more information about AUC Little Logic devices, see Applications of Texas Instruments AUC Sub-1-V Little Logic Devices, SCEA027.

filter

기타 OR 게이트 찾기

다운로드 스크립트와 함께 비디오 보기 동영상

관심 가지실만한 유사 제품

open-in-new

대안 비교

비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀

SN74AUP1G14

활성

슈미트 트리거 입력을 지원하는 단일 0.8V~3.6V 저전력 인버터 Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA

기술 자료

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=TI에서 선정한 이 제품의 인기 문서

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17개 모두 보기

	유형	직함		날짜
*	Data sheet	SN74AUC1G32 Single 2-Input Positive-OR Gate datasheet (Rev. P)	PDF \| HTML	2017/06/08
	Selection guide	Little Logic Guide 2018 (Rev. G)		2018/07/06
	Selection guide	Logic Guide (Rev. AB)		2017/06/12
	Application note	How to Select Little Logic (Rev. A)		2016/07/26
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		2015/12/02
	User guide	LOGIC Pocket Data Book (Rev. B)		2007/01/16
	Product overview	Design Summary for WCSP Little Logic (Rev. B)		2004/11/04
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		2004/07/08
	Application note	Selecting the Right Level Translation Solution (Rev. A)		2004/06/22
	User guide	Signal Switch Data Book (Rev. A)		2003/11/14
	Application note	Designing With TI Ultra-Low-Voltage CMOS (AUC) Octals and Widebus Devices		2003/03/21
	User guide	AUC Data Book, January 2003 (Rev. A)		2003/01/01
	Application note	Texas Instruments Little Logic Application Report		2002/11/01
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		2002/08/29
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards		2002/06/13
	More literature	STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS		2002/03/27
	More literature	AUC Product Brochure (Rev. A)		2002/03/18

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

5-8-LOGIC-EVM — 5핀~8핀 DCK, DCT, DCU, DRL 및 DBV 패키지용 일반 논리 평가 모듈

5~8핀 수의 DCK, DCT, DCU, DRL 또는 DBV 패키지가 있는 모든 디바이스를 지원하도록 설계된 유연한 EVM.

사용 설명서: PDF

TI.com에서 구매 불가

시뮬레이션 모델

HSPICE Model of SN74AUC1G32

SCEJ134.ZIP (42 KB) - HSpice Model

다운로드

시뮬레이션 모델

SN74AUC1G32 Behavioral SPICE Model

SCEM720.ZIP (7 KB) - PSpice Model

다운로드

시뮬레이션 모델

SN74AUC1G32 IBIS Model (Rev. B)

SCEM224B.ZIP (55 KB) - IBIS Model

다운로드

레퍼런스 디자인

TIDEP0036 — 효율적인 OPUS 코덱 솔루션 구현을 위해 TMS320C6657을 사용한 레퍼런스 설계

The TIDEP0036 reference design provides an example of the ease of running TI optimized Opus encoder/decoder on the TMS320C6657 device. Since Opus supports a a wide range of bit rates, frame sizes and sampling rates, all with low delay, it has applicability for voice communications, networked audio (...)

Design guide: PDF

회로도: PDF