SN74AVC1T45

Name: SN74AVC1T45
Brand: TI
SKU: SN74AVC1T45
Price: 0.141 USD

활성

구성 가능한 전압 레벨 변환 및 3상 출력을 지원하는 단일 비트 듀얼 공급 버스 트랜시버

지금 주문

데이터 시트

document-pdfAcrobat SN74AVC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and 3-State Outputs datasheet (Rev. I) (영어) PDF | HTML

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대안 비교

비교 대상 장치보다 업그레이드된 기능을 지원하는 즉각적 대체품

SN74AXC1T45

활성

싱글 비트 듀얼 공급 버스 트랜시버 Pin-to-pin upgrade with a wider voltage range and improved performance

SN74AVC1T45

활성

데이터 시트

지금 주문

제품 상세 정보

Technology family

AVC

Applications

GPIO

Bits (#)

1

High input voltage (min) (V)

0.78

High input voltage (max) (V)

3.6

Vout (min) (V)

1.2

Vout (max) (V)

3.6

Data rate (max) (Mbps)

500

IOH (max) (mA)

-12

IOL (max) (mA)

12

Supply current (max) (µA)

20

Features

Output enable, Overvoltage tolerant inputs, Partial power down (Ioff)

Input type

Standard CMOS

Output type

3-State, Balanced CMOS, Push-Pull

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

AVC

Applications

GPIO

Bits (#)

1

High input voltage (min) (V)

0.78

High input voltage (max) (V)

3.6

Vout (min) (V)

1.2

Vout (max) (V)

3.6

Data rate (max) (Mbps)

500

IOH (max) (mA)

-12

IOL (max) (mA)

12

Supply current (max) (µA)

20

Features

Output enable, Overvoltage tolerant inputs, Partial power down (Ioff)

Input type

Standard CMOS

Output type

3-State, Balanced CMOS, Push-Pull

Rating

Catalog

Operating temperature range (°C)

-40 to 85

DSBGA (YZP)

6

2.1875 mm² 1.75 x 1.25

SOT-23 (DBV)

6

8.12 mm² 2.9 x 2.8

SOT-5X3 (DRL)

6

2.56 mm² 1.6 x 1.6

SOT-SC70 (DCK)

6

4.2 mm² 2 x 2.1

Available in the Texas Instruments NanoFree™ package
Fully configurable dual-rail design allows each port to operate over the full 1.2V to 3.6V power-supply range
VCC isolation feature – if either VCC input is at GND, then both ports are in the high-impedance state
DIR input circuit referenced to VCCA
±12mA output drive at 3.3V
I/Os are 4.6V tolerant
Ioff supports partial-power-down mode operation
Typical maximum data rates
- 500Mbps (1.8V to 3.3V translation)
- 320Mbps (<1.8V to 3.3V translation)
- 320Mbps (translate to 2.5V or 1.8V)
- 280Mbps (translate to 1.5V)
- 240Mbps (translate to 1.2V)
Latch-up performance exceeds 100mA per JESD 78, Class II
ESD protection exceeds JESD 22
- ±2000V Human Body Model (A114-A)
- 200V Machine Model (A115-A)
- ±1000V Charged-Device Model (C101)

Available in the Texas Instruments NanoFree™ package
Fully configurable dual-rail design allows each port to operate over the full 1.2V to 3.6V power-supply range
VCC isolation feature – if either VCC input is at GND, then both ports are in the high-impedance state
DIR input circuit referenced to VCCA
±12mA output drive at 3.3V
I/Os are 4.6V tolerant
Ioff supports partial-power-down mode operation
Typical maximum data rates
- 500Mbps (1.8V to 3.3V translation)
- 320Mbps (<1.8V to 3.3V translation)
- 320Mbps (translate to 2.5V or 1.8V)
- 280Mbps (translate to 1.5V)
- 240Mbps (translate to 1.2V)
Latch-up performance exceeds 100mA per JESD 78, Class II
ESD protection exceeds JESD 22
- ±2000V Human Body Model (A114-A)
- 200V Machine Model (A115-A)
- ±1000V Charged-Device Model (C101)

This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVC1T45 is optimized to operate with VCCA/VCCB set at 1.4V to 3.6V. It is operational with VCCA/VCCB as low as 1.2V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2V to 3.6V. This allows for universal low-voltage, bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC1T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC1T45 is designed so that the DIR input is powered by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature is designed so that if either VCC input is at GND, then both ports are in the high-impedance state.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVC1T45 is optimized to operate with VCCA/VCCB set at 1.4V to 3.6V. It is operational with VCCA/VCCB as low as 1.2V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2V to 3.6V. This allows for universal low-voltage, bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC1T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC1T45 is designed so that the DIR input is powered by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature is designed so that if either VCC input is at GND, then both ports are in the high-impedance state.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

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19개 모두 보기

	유형	직함		날짜
*	Data sheet	SN74AVC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and 3-State Outputs datasheet (Rev. I)	PDF \| HTML	2024/03/20
	Application note	Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators	PDF \| HTML	2024/07/12
	Application note	Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A)	PDF \| HTML	2024/07/03
	EVM User's guide	Generic AVC and LVC Direction Controlled Translation EVM (Rev. B)		2021/07/30
	Selection guide	Voltage Translation Buying Guide (Rev. A)		2021/04/15
	Selection guide	Logic Guide (Rev. AB)		2017/06/12
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		2015/12/02
	Application note	Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B)		2015/04/30
	Test report	TI Power Reference Design for Xilinx® Artix®-7 (AC701)		2014/05/12
	User guide	PMP7977 User's Guide		2013/09/11
	User guide	LOGIC Pocket Data Book (Rev. B)		2007/01/16
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		2004/07/08
	Application note	Selecting the Right Level Translation Solution (Rev. A)		2004/06/22
	More literature	LCD Module Interface Application Clip		2003/05/09
	User guide	AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C)		2002/08/20
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards		2002/06/13
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)		2002/05/22
	Application note	Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B)		1999/07/07
	Application note	AVC Logic Family Technology and Applications (Rev. A)		1998/08/26

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