이 제품의 최신 버전이 있습니다
비교 대상 장치보다 업그레이드된 기능을 지원하는 드롭인 대체품
SN74AVC2T245
- Each Channel Has Independent Direction Control
- Control Inputs VIH/VIL Levels Are Referenced to
VCCA Voltage - Fully Configurable Dual-Rail Design Allows Each
Port to Operate Over the Full 1.2 V to
3.6 V Power-Supply Range - I/Os Are 4.6 V Tolerant
- Ioff Supports Partial-Power-Down Mode Operation
- VCC Isolation Feature - If Either VCC Input is at
GND, Both Ports are in High-Impedance State - Typical Data Rates
- 500 Mbps (1.8 V to 3.3 V Level-Shifting)
- 320 Mbps (<1.8 V to 3.3 V Level-Shifting)
- 320 Mbps (Translate to 2.5 V or 1.8 V)
- 280 Mbps (Translate to 1.5 V)
- 240 Mbps (Translate to 1.2 V)
- Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II - ESD Protection Exceeds JESD 22
- 5000 V Human-Body Model (A114-A)
- 200 V Machine Model (A115-A)
- 1500 V Charged-Device Model (C101)
This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.
The SN74AVC2T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode . The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.
The SN74AVC2T245 control pins (DIR1, DIR2, and OE) are supplied by VCCA.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE must be connected to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
기술 자료
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
AXC2T-SMALLPKGEVM — DTM 및 RSW 패키지 장치용 AXC2T 소형 패키지 평가 모듈
EVMK2GX — 66AK2Gx 1GHz 평가 모듈
The EVMK2GX (also known as "K2G") 1GHz evaluation module (EVM) enables developers to immediately start evaluating the 66AK2Gx processor family, and to accelerate the development of audio, industrial motor control, smart grid protection and other high reliability, real-time compute intensive (...)
TIDEP0050 — EnDat 2.2 시스템 레퍼런스 설계
TIDA-00403 — TLV320AIC3268 miniDSP 코덱을 사용한 초음파 거리 측정 레퍼런스 디자인
패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
---|---|---|
UQFN (RSW) | 10 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치