SN74F299

Name: SN74F299
Brand: TI
SKU: SN74F299
Price: 0.327 USD

활성

범용 시프트/저장소 레지스터

지금 주문

데이터 시트

document-pdfAcrobat SN54F299, SN74F299 datasheet (Rev. B) (영어)

SN74F299

활성

데이터 시트

지금 주문

제품 상세 정보

Configuration

Universal

Bits (#)

8

Technology family

F

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

Bipolar

Output type

3-State

Clock frequency (MHz)

70

IOL (max) (mA)

24

IOH (max) (mA)

-3

Supply current (max) (µA)

95000

Features

High speed (tpd 10-50ns)

Operating temperature range (°C)

0 to 70

Rating

Catalog

Configuration

Universal

Bits (#)

8

Technology family

F

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

Bipolar

Output type

3-State

Clock frequency (MHz)

70

IOL (max) (mA)

24

IOH (max) (mA)

-3

Supply current (max) (µA)

95000

Features

High speed (tpd 10-50ns)

Operating temperature range (°C)

0 to 70

Rating

Catalog

PDIP (N)

20

228.702 mm² 24.33 x 9.4

SOIC (DW)

20

131.84 mm² 12.8 x 10.3

Four Modes of Operation:
- Hold (Store)
- Shift Right
- Shift Left
- Load Data
Operates With Outputs Enabled or at High Impedance
3-State Outputs Drive Bus Lines Directly
Can Be Cascaded for N-Bit Word Lengths
Direct Overriding Clear
Applications:
- Stacked or Push-Down Registers
- Buffer Storage
- Accumulator Registers

Four Modes of Operation:
- Hold (Store)
- Shift Right
- Shift Left
- Load Data
Operates With Outputs Enabled or at High Impedance
3-State Outputs Drive Bus Lines Directly
Can Be Cascaded for N-Bit Word Lengths
Direct Overriding Clear
Applications:
- Stacked or Push-Down Registers
- Buffer Storage
- Accumulator Registers

These 8-bit universal shift/storage registers feature multiplexed I/O ports to achieve full 8-bit data handling in a single 20-pin package. Two function-select (S0, S1) inputs and two output-enable (OE1\, OE2\) inputs can be used to choose the modes of operation listed in the function table.

Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs in a high-impedance state and permits data that is applied on the I/O ports to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs when the clear (CLR\) input is low. Taking either OE1\ or OE2\ high disables the outputs but has no effect on clearing, shifting, or storage of data.

These 8-bit universal shift/storage registers feature multiplexed I/O ports to achieve full 8-bit data handling in a single 20-pin package. Two function-select (S0, S1) inputs and two output-enable (OE1\, OE2\) inputs can be used to choose the modes of operation listed in the function table.

Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs in a high-impedance state and permits data that is applied on the I/O ports to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs when the clear (CLR\) input is low. Taking either OE1\ or OE2\ high disables the outputs but has no effect on clearing, shifting, or storage of data.

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