SN74GTL2010
- Provides Bidirectional Voltage Translation With No Direction Control Required
- Allows Voltage Level Translation From 1 V up to 5 V
- Provides Direct Interface With GTL, GTL+, LVTTL/TTL, and 5-V CMOS Levels
- Low On-State Resistance Between Input and Output Pins (Sn/Dn)
- Supports Hot Insertion
- No Power Supply Required — Will Not Latch Up
- 5-V-Tolerant Inputs
- Low Standby Current
- Flow-Through Pinout for Ease of Printed Circuit Board Trace Routing
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-4)
- 1000-V Charged-Device Model (C101)
- APPLICATIONS
- Bidirectional or Unidirectional Applications Requiring Voltage-Level Translation From Any Voltage (1 V to 5 V) to Any Voltage (1 V to 5 V)
- Low Voltage Processor I2C Port Translation to 3.3-V and/or 5-V I2C Bus Signal Levels
- GTL/GTL+ Translation to LVTTL/TTL Signal Levels
The GTL2010 provides ten NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor (SREF and DREF). The low ON-state resistance of the switch allows connections to be made with minimal propagation delay. With no direction control pin required, the device allows bidirectional voltage translations any voltage (1 V to 5 V) to any voltage (1 V to 5 V).
When the Sn or Dn port is LOW, the clamp is in the ON state and a low-resistance connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is HIGH, the voltage on the Sn port is limited to the voltage set by the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to VCC by the pullup resistors.
All transistors in the GTL2010 have the same electrical characteristics, and there is minimal deviation from one output to another in voltage or propagation delay. This offers superior matching over discrete transistor voltage-translation solutions where the fabrication of the transistors is not symmetrical. With all transistors being identical, the reference transistor (SREF/DREF) can be located on any of the other ten matched Sn/Dn transistors, allowing for easier board layout. The translator transistors with integrated ESD circuitry provides excellent ESD protection.
기술 자료
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈
14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.
14-24-NL-LOGIC-EVM — 14핀~24핀 비 리드 패키지용 로직 제품 일반 평가 모듈
14-24-NL-LOGIC-EVM은 14핀~24핀 BQA, BQB, RGY, RSV, RJW 또는 RHL 패키지가 있는 로직 또는 변환 디바이스를 지원하도록 설계된 유연한 평가 모듈(EVM)입니다.
패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
---|---|---|
TSSOP (PW) | 24 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치