홈 로직 및 전압 변환 로직 게이트 NOR 게이트
홈
로직 및 전압 변환
로직 게이트
NOR 게이트

SN74HC02-EP

활성

Enhanced product 4-ch, 2-input, 2-V to 6-V NOR gate

지금 주문
데이터 시트

SN74HC02-EP

활성
데이터 시트 지금 주문

제품 상세 정보

Technology family HC Number of channels 4 Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Inputs per channel 2 IOL (max) (mA) 4 IOH (max) (mA) -4 Output type Push-Pull Input type Standard CMOS Features High speed (tpd 10- 50ns) Data rate (max) (Mbps) 28 Rating HiRel Enhanced Product Operating temperature range (°C) -40 to 125
Technology family HC Number of channels 4 Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Inputs per channel 2 IOL (max) (mA) 4 IOH (max) (mA) -4 Output type Push-Pull Input type Standard CMOS Features High speed (tpd 10- 50ns) Data rate (max) (Mbps) 28 Rating HiRel Enhanced Product Operating temperature range (°C) -40 to 125
TSSOP (PW) 14 32 mm² 5 x 6.4
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of Up To –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • 2-V to 6-V VCC Operation
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 20-µA Max ICC
  • Typical tpd = 8 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of Up To –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • 2-V to 6-V VCC Operation
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 20-µA Max ICC
  • Typical tpd = 8 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

The SN74HC02 contains four independent 2-input NOR gates. It performs the Boolean function Y = (A + B)\ or Y = A\ • B\ in positive logic.

The SN74HC02 contains four independent 2-input NOR gates. It performs the Boolean function Y = (A + B)\ or Y = A\ • B\ in positive logic.
filter 기타 NOR 게이트 찾기
다운로드 스크립트와 함께 비디오 보기 동영상

관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
SN74LV4T02-EP 활성 향상된 제품, 통합 레벨 시프터가 있는 4채널 2입력 NOR 게이트 Voltage range (1.65V to 5.5V), voltage translation capable

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
16개 모두 보기
유형 직함 날짜
* Data sheet SN74HC02-EP datasheet (Rev. A) 2004/01/06
* VID SN74HC02-EP VID V6204687 2016/06/21
* Radiation & reliability report SN74HC02QPWREP Reliability Report 2013/09/05
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note Designing With Logic (Rev. C) 1997/06/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 1996/05/01
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996/04/01

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

패키지 핀 CAD 기호, 풋프린트 및 3D 모델
TSSOP (PW) 14 Ultra Librarian
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

포럼 주제 모두 보기(영문)

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

동영상