SN74LS293

Name: SN74LS293
Brand: TI
SKU: SN74LS293
Price: 1.22 USD

활성

4비트 이진 카운터

지금 주문

데이터 시트

document-pdfAcrobat Decade And 4-Bit Binary Counters datasheet (영어)

SN74LS293

활성

데이터 시트

지금 주문

제품 상세 정보

Function

Counter

Bits (#)

4

Technology family

LS

Supply voltage (min) (V)

4.75

Supply voltage (max) (V)

5.25

Input type

Bipolar

Output type

Push-Pull

Features

High speed (tpd 10-50ns)

Operating temperature range (°C)

0 to 70

Rating

Catalog

Function

Counter

Bits (#)

4

Technology family

LS

Supply voltage (min) (V)

4.75

Supply voltage (max) (V)

5.25

Input type

Bipolar

Output type

Push-Pull

Features

High speed (tpd 10-50ns)

Operating temperature range (°C)

0 to 70

Rating

Catalog

PDIP (N)

14

181.42 mm² 19.3 x 9.4

SOIC (D)

14

51.9 mm² 8.65 x 6

'290, 'LS290...DECADE COUNTERS

'293, 'LS293...4–BIT BINARY COUNTERS

GND and V_CC on Corner Pins (Pins 7 and 14 Respectively)

'290, 'LS290...DECADE COUNTERS

'293, 'LS293...4–BIT BINARY COUNTERS

GND and V_CC on Corner Pins (Pins 7 and 14 Respectively)

The SN54290/SN74290, SN54LS290/SN74LS290, SN54293/SN74293, and SN54LS293/SN74LS293 counters are electrically and functionally identical to the SN5490A/SN7490A, SN54LS90/SN74LS90, SN5493A/SN7493A, and SN54LS93/SN74LS93, respectively. Only the arrangement of the terminals has been changed for the '290, 'LS290, '293, and 'LS293.

Each of these monolithic counters contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-five for the '290 and 'LS290 and divide-by-eight for the '293 and 'LS293.

All of these counters have a gated zero reset and the '290 and 'LS290 also have gated set-to-nine inputs for use in BCD nine's complement applications.

To use the maximum count length (decade or four-bit binary) of these counters, the B input is connected to the Q_A output. The input count pulses are applied to input A and the outputs are as described in the appropriate function table. A symmetrical divide-by-ten count can be obtained from the '290 and 'LS290 counters by connecting the Q_D output to the A input and applying the input count to the B input which gives a divide-by-ten square wave at output Q_A.

The SN54290/SN74290, SN54LS290/SN74LS290, SN54293/SN74293, and SN54LS293/SN74LS293 counters are electrically and functionally identical to the SN5490A/SN7490A, SN54LS90/SN74LS90, SN5493A/SN7493A, and SN54LS93/SN74LS93, respectively. Only the arrangement of the terminals has been changed for the '290, 'LS290, '293, and 'LS293.

Each of these monolithic counters contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-five for the '290 and 'LS290 and divide-by-eight for the '293 and 'LS293.

All of these counters have a gated zero reset and the '290 and 'LS290 also have gated set-to-nine inputs for use in BCD nine's complement applications.

To use the maximum count length (decade or four-bit binary) of these counters, the B input is connected to the Q_A output. The input count pulses are applied to input A and the outputs are as described in the appropriate function table. A symmetrical divide-by-ten count can be obtained from the '290 and 'LS290 counters by connecting the Q_D output to the A input and applying the input count to the B input which gives a divide-by-ten square wave at output Q_A.

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