SN74LS590

Name: SN74LS590
Brand: TI
SKU: SN74LS590
Price: 5.262 USD

활성

출력 레지스터 및 3상 출력을 지원하는 8비트 이진 카운터

지금 주문

데이터 시트

document-pdfAcrobat 8-Bit Binary Counters With Output Registers datasheet (영어)

SN74LS590

활성

데이터 시트

지금 주문

제품 상세 정보

Function

Counter

Bits (#)

8

Technology family

LS

Supply voltage (min) (V)

4.75

Supply voltage (max) (V)

5.25

Input type

Bipolar

Output type

3-State

Features

High speed (tpd 10-50ns)

Operating temperature range (°C)

0 to 70

Rating

Catalog

Function

Counter

Bits (#)

8

Technology family

LS

Supply voltage (min) (V)

4.75

Supply voltage (max) (V)

5.25

Input type

Bipolar

Output type

3-State

Features

High speed (tpd 10-50ns)

Operating temperature range (°C)

0 to 70

Rating

Catalog

PDIP (N)

16

181.42 mm² 19.3 x 9.4

SOIC (D)

16

59.4 mm² 9.9 x 6

SOP (NS)

16

79.56 mm² 10.2 x 7.8

8-Bit Counter with Register
Parallel Register Outputs
Choice of 3-State ('LS590) or Open-Collector ('LS591) Register Outputs
Guaranteed Counter Frequency:DC to 20 MHz

8-Bit Counter with Register
Parallel Register Outputs
Choice of 3-State ('LS590) or Open-Collector ('LS591) Register Outputs
Guaranteed Counter Frequency:DC to 20 MHz

These devices each contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features a direct clear input CCLR\ and a count enable input CCKEN\. For cascading, a ripple carry output RCO\ is provided. Expansion is easily accomplished for two stages by connecting RCO\ of the first stage to CCKEN\ of the second stage. Cascading for larger count chains can be accomplished by connecting RCO\ of each stage to CCK of the following stage.

Both the counter and register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the counter state will always be one count ahead of the register. Internal circuitry prevents clocking from the clock enable.

These devices each contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features a direct clear input CCLR\ and a count enable input CCKEN\. For cascading, a ripple carry output RCO\ is provided. Expansion is easily accomplished for two stages by connecting RCO\ of the first stage to CCKEN\ of the second stage. Cascading for larger count chains can be accomplished by connecting RCO\ of each stage to CCK of the following stage.

Both the counter and register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the counter state will always be one count ahead of the register. Internal circuitry prevents clocking from the clock enable.

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