SN74LS595

Name: SN74LS595
Brand: TI
SKU: SN74LS595
Price: 5.555 USD

활성

출력 레지스터가 포함된 직렬 입력 시프트 레지스터

지금 주문

데이터 시트

document-pdfAcrobat 8-Bit Shift Registers With Output Latches datasheet (영어)

SN74LS595

활성

데이터 시트

지금 주문

제품 상세 정보

Configuration

Serial-in, Parallel-out

Bits (#)

8

Technology family

LS

Supply voltage (min) (V)

4.75

Supply voltage (max) (V)

5.25

Input type

Bipolar

Output type

Push-Pull

Clock frequency (MHz)

25

IOL (max) (mA)

24

IOH (max) (mA)

-2.6

Supply current (max) (µA)

65000

Features

High speed (tpd 10-50ns), Output register

Operating temperature range (°C)

0 to 70

Rating

Catalog

Configuration

Serial-in, Parallel-out

Bits (#)

8

Technology family

LS

Supply voltage (min) (V)

4.75

Supply voltage (max) (V)

5.25

Input type

Bipolar

Output type

Push-Pull

Clock frequency (MHz)

25

IOL (max) (mA)

24

IOH (max) (mA)

-2.6

Supply current (max) (µA)

65000

Features

High speed (tpd 10-50ns), Output register

Operating temperature range (°C)

0 to 70

Rating

Catalog

PDIP (N)

16

181.42 mm² 19.3 x 9.4

SOIC (D)

16

59.4 mm² 9.9 x 6

8-Bit Serial-In, Parallel-Out Shift Registers with Storage
Choice of 3-State ('LS595) or Open-Collector ('LS596) Parallel Outputs
Shift Register Has Direct Clear
Accurate Shift Frequency:DC to 20 MHz

8-Bit Serial-In, Parallel-Out Shift Registers with Storage
Choice of 3-State ('LS595) or Open-Collector ('LS596) Parallel Outputs
Shift Register Has Direct Clear
Accurate Shift Frequency:DC to 20 MHz

These devices each contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state ('LS595) or open-collector ('LS596) outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output pins for cascading.

Both the shift register and storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register state will always be one clock pulse ahead of the storage register.

These devices each contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state ('LS595) or open-collector ('LS596) outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output pins for cascading.

Both the shift register and storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register state will always be one clock pulse ahead of the storage register.

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