SN74LV573AT

Name: SN74LV573AT
Brand: TI
SKU: SN74LV573AT
Price: 0.295 USD

활성

3상 출력을 지원하는 8진 트랜스페어런스 D형 래치

지금 주문

데이터 시트

document-pdfAcrobat SN74LV573AT datasheet (Rev. C) (영어)

SN74LV573AT

활성

데이터 시트

지금 주문

제품 상세 정보

Number of channels

8

Technology family

LV-AT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

3-State

Clock frequency (max) (MHz)

70

IOL (max) (mA)

16

IOH (max) (mA)

-16

Supply current (max) (µA)

20

Features

Balanced outputs, Flow-through pinout, High speed (tpd 10-50ns), Partial power down (Ioff)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of channels

8

Technology family

LV-AT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

3-State

Clock frequency (max) (MHz)

70

IOL (max) (mA)

16

IOH (max) (mA)

-16

Supply current (max) (µA)

20

Features

Balanced outputs, Flow-through pinout, High speed (tpd 10-50ns), Partial power down (Ioff)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

SOIC (DW)

20

131.84 mm² 12.8 x 10.3

TSSOP (PW)

20

41.6 mm² 6.5 x 6.4

Inputs Are TTL-Voltage Compatible
4.5-V to 5.5-V V_CC Operation
Typical t_pd = 5.1 ns at 5 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 5 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2.3 V at V_CC = 5 V, T_A = 25°C
Supports Mixed-Mode Voltage Operation on All Ports
I_off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Inputs Are TTL-Voltage Compatible
4.5-V to 5.5-V V_CC Operation
Typical t_pd = 5.1 ns at 5 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 5 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2.3 V at V_CC = 5 V, T_A = 25°C
Supports Mixed-Mode Voltage Operation on All Ports
I_off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

The SN74LV573AT is an octal transparent D-type latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

To ensure the high-impedance state during power up or power down, OE shall be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74LV573AT is an octal transparent D-type latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

To ensure the high-impedance state during power up or power down, OE shall be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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