SN74LV8154
- Can Be Used as Two 16-Bit Counters or a Single 32-Bit Counter
- 8-bit counter read bus
- 2-V to 5.5-V VCC Operation
- Maximum tpd of 25 ns at 5 V (RCLK to Y)
- Typical VOLP (Output Ground Bounce)
< 0.7 V at VCC = 5 V, TA = 25°C - Typical VOHV (Output VOH Undershoot)
> 4.4 V at VCC = 5 V, TA = 25°C - Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 250 mA
Per JESD 17 - ESD Protection Exceeds JESD 22
- 2000-V Human Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
The SN74LV8154 device is a dual 16-bit binary counter with 3-state output registers, designed for 2-V to 5.5-V VCC operation.
The counters have dedicated clock inputs. The counters share a clocked storage register to sample and save the counter contents. Both counters share an asynchronous clear input. The 32-bit storage register can be mapped on the output bus 8-bits at a time. Four bus reads are needed to access the contents of both stored counts. The two counters can be chained by connecting CLKBEN to RCOA. All clocks are positive edge triggered. All other inputs are active low.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
관심 가지실만한 유사 제품
비교 대상 장치와 유사한 기능
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | SN74LV8154 Dual 16-Bit Binary Counters With 3-State Output Registers datasheet (Rev. B) | PDF | HTML | 2020/04/27 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈
14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| PDIP (N) | 20 | Ultra Librarian |
| TSSOP (PW) | 20 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치